Stacked Memory Interposer with Buffer Chip for High Bandwidth
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Solution Overview
Problem
There is a trade-off in computing systems between memory capacity, bandwidth, and energy efficiency, as adding multiple dual in-line memory modules (DIMMs) increases capacity but reduces data transfer rate and bandwidth, making it difficult to achieve high capacity and high bandwidth in an energy-efficient manner.
Innovation Solution
A memory device comprising a semiconductor interposer, multiple memory stacks, and a buffer chip, where the memory stacks are configured as a single stack and electrically coupled to the interposer, and the buffer chip is connected via wide bit-width data buses to both the memory stacks and a processor data bus, allowing for high-capacity and high-bandwidth operation while being energy efficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DIMMs are added to expand memory capacity, then data capacity increases, but data transfer rate and bandwidth are significantly reduced
Solution Approach 1:
The patent transitions from a two-dimensional memory architecture (multiple DIMMs on a bus) to a three-dimensional architecture using stacked memory dies with through-silicon vias (TSVs). This vertical stacking enables high capacity while maintaining short signal paths and high transfer rates by eliminating the bandwidth limitations of horizontal bus expansion.
Solution Approach 2:
The patent introduces a buffer chip as an intermediary between the processor and stacked memory dies. The buffer chip manages data flow and protocol conversion, enabling efficient communication between the high-speed memory stacks and the processor while maintaining high bandwidth and capacity simultaneously.
2Quantity of substance
If multiple DIMMs are connected to increase memory capacity, then capacity expands from 32 GB to 128 GB, but operating frequency is reduced from 1 GHz to 666 MHz
Solution Approach 1:
The patent uses vertical stacking of memory dies with TSVs to achieve high capacity without increasing the number of devices on the memory bus. This dimensional change allows each stack to operate at high frequencies independently, avoiding the frequency reduction that occurs when multiple DIMMs share a bus.
Solution Approach 2:
The patent divides the memory system into multiple independent stacked memory modules, each with its own buffer chip and data paths. This segmentation allows parallel operation of multiple stacks, maintaining high operating frequencies while achieving high total capacity through aggregated bandwidth.
3Quantity of substance
If traditional DIMM architecture is used for high capacity, then memory capacity increases, but form-factor becomes large and energy efficiency decreases
Solution Approach 1:
The patent employs three-dimensional stacked memory architecture with vertical interconnects, dramatically reducing the form-factor compared to traditional horizontal DIMM layouts. The compact vertical structure achieves high capacity in a small footprint while reducing energy consumption through shorter signal paths and lower capacitance.
Solution Approach 2:
The patent changes the physical and electrical parameters of the memory system by using TSVs for vertical interconnection and implementing a buffer chip architecture. These parameter changes enable high capacity in a compact form-factor with improved energy efficiency due to reduced signal path lengths and optimized data flow management.
Data Source
AI summary
A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack. The buffer chip is electrically coupled to the first memory stack via a first data bus, electrically coupled to the second memory stack via a second data bus, and electrically coupled to a processor data bus that is configured for transmitting signals between the buffer chip and a processor chip. Such a memory device can have high data capacity and still operate at a high data transfer rate in an energy efficient manner.