Stacked Memory Device Using Interposer Chips and TSVs
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase integration density and reduce production costs while maintaining high-speed performance, which is hindered by the limitations of existing IC packaging techniques and the need for vertical integration of multiple chips.
Innovation Solution
A semiconductor memory device is designed with a stacked combination of memory chips and interposer chips, where each interposer chip is larger than the corresponding memory chip and connected via through silicon vias (TSVs) to form multiple internal signal paths, allowing for efficient data communication between memory chips and a buffer chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are stacked vertically to increase integration density, then packaging density is improved, but device complexity increases due to the need for interposer chips and TSV connections
Solution Approach 1:
The patent implements a stacked memory device structure where memory chips are nested vertically on interposer chips, forming a multi-layer configuration. Each memory chip is mounted on an interposer chip, and multiple interposer chips are stacked vertically with TSV connections between them, creating a nested arrangement that increases integration density while managing complexity through modular design
Solution Approach 2:
The patent introduces interposer chips as intermediary elements between memory chips and the substrate. These interposer chips provide connection interfaces and routing pathways, mediating the complex interconnections between multiple memory chips and reducing the overall system complexity by centralizing the connection management in dedicated intermediary components
2Speed
If TSVs are formed proximate to edges of interposer chips to create multiple internal signal paths, then data communication speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions signal paths from a planar two-dimensional layout to a three-dimensional vertical structure by forming TSVs that extend through the interposer chips in the vertical dimension. This allows multiple signal paths to be packed more densely by utilizing the vertical space between stacked interposer chips, thereby increasing data transfer capacity while managing the complexity through spatial reorganization
Data Source
AI summary
A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.