Stacked Memory Subsystem with I/O Die for Fewer Signal Lines
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Solution Overview
Problem
Existing computing systems face challenges in efficiently connecting host devices and memory apparatuses as advanced packaging technologies increase the number of signal transmission lines, particularly when the host device and memory apparatus are manufactured as chiplets, necessitating more efficient architectures for data transmission.
Innovation Solution
A memory subsystem is introduced, featuring an I/O die with conductive pads and stacked memory structures connected via vertical wires, and a circuit board with packages that facilitate parallel data communication, eliminating the need for additional circuits like SerDes and enhancing data bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the host device and memory apparatus are manufactured as chiplets with advanced packaging technologies, then integration flexibility is improved, but the number of signal transmission lines electrically connecting them increases
Solution Approach 1:
The patent introduces a vertical stacking dimension by placing the I/O die between the host device and memory apparatus in a three-dimensional arrangement. The I/O die receives parallel data signals from the host device through conductive pads on its first surface and transmits serialized data to the memory apparatus through vertical wires extending from its second surface. This vertical dimension allows efficient signal transmission with reduced line count compared to planar chiplet connections.
Data Source
AI summary
A memory subsystem includes an I/O die, a host device, and a stacked memory structure. The I/O die includes a first surface and a second surface. The host device is stacked on the first surface of the I/O die to be at least partially bonded thereto. The stacked memory structure is stacked on the first surface of the I/O die to be at least partially bonded thereto. The I/O die includes a plurality of conductive pads arranged on the first surface. The stacked memory structure includes a plurality of memory dies stacked in a shingled manner so that a plurality of bonding pads is exposed, and a plurality of vertical wires respectively connecting the bonding pads of the plurality of memory dies to the plurality of conductive pads. The host device and the stacked memory structure is configured to interface with each other through the I/O die.