3D Semiconductor Memory Stacks With Isolated Decoder Blocks
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Solution Overview
Problem
Conventional three-dimensional semiconductor memory devices face limitations in integration and reliability due to shared common pass transistors, leading to increased memory device size and decreased performance, as well as potential signal noise.
Innovation Solution
The configuration of separate decoder circuit parts and pass transistors allows for independent electrical signal application to each memory block, increasing practical storage space and reducing memory block size, thereby enhancing performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate decoder circuit parts and pass transistors are used for each memory block, then reliability and performance are improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent memory blocks, each with its own dedicated decoder circuit part and pass transistors. This segmentation isolates signal paths between blocks, preventing signal noise interference and improving reliability, while maintaining manageable complexity through modular design
Solution Approach 2:
The decoder circuit parts and pass transistors are extracted from a shared common configuration and assigned to individual memory blocks. This extraction eliminates the source of signal noise that occurred when multiple blocks shared common pass transistors, thereby improving reliability without significantly increasing overall device complexity
2Productivity
If memory blocks are reduced in size through separate decoder circuits, then performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the decoder circuits and pass transistors into separate units for each memory block, the patent enables smaller, more efficient memory block sizes that improve performance. The modular segmented structure allows for standardized fabrication processes that can maintain precision requirements
3Quantity of substance
If three-dimensional stacked memory structure is implemented, then integration is increased, but signal noise and reliability issues arise
Solution Approach 1:
The three-dimensional stacked memory structure is divided into multiple independent memory blocks with separate decoder circuits. This segmentation allows high integration through vertical stacking while preventing signal noise interference between blocks, as each block has its own isolated signal paths and pass transistors
Solution Approach 2:
The patent transitions from two-dimensional planar memory architecture to three-dimensional stacked architecture by vertically arranging multiple memory blocks. This dimensional change increases integration capacity while the separate decoder circuit configuration for each block mitigates signal noise issues that would otherwise arise from the denser three-dimensional configuration
Data Source
AI summary
A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.