3D Stacked NAND Memory Arrays to Reduce Gate-Line Coupling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating multiple memory cell arrays and circuit chips while maintaining optimal electrical connectivity and reducing electrical coupling between select gate lines, which affects performance and efficiency.
Innovation Solution
A semiconductor memory device is designed with a three-dimensional stacked NAND flash memory configuration, where array chips are stacked and connected via a circuit chip, with shared bit lines and word lines but independent select gate lines, allowing for efficient electrical coupling and reduced interference between select gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cell arrays are integrated in a three-dimensional stacked configuration, then storage capacity is improved, but electrical coupling between select gate lines increases causing interference
Solution Approach 1:
The memory device is divided into multiple independent array chips (first array chip, second array chip, etc.) stacked in the third direction. Each array chip contains its own memory cell arrays with select gate lines that are electrically isolated from other chips. This segmentation physically separates the select gate lines into different electrical domains, reducing parasitic coupling and interference while maintaining high storage capacity through vertical stacking.
Solution Approach 2:
Circuit chips are introduced as intermediary components between array chips to establish electrical connections. The circuit chips contain bit line connection circuits that mediate the electrical coupling between memory cell arrays on different array chips. This intermediary structure allows controlled electrical connectivity for data access while isolating the select gate lines, preventing direct parasitic coupling between adjacent memory cell arrays.
2Reliability
If array chips are stacked and connected via circuit chip with shared bit lines and word lines, then electrical connectivity is improved, but interference between select gate lines increases
Solution Approach 1:
Select gate lines are segmented into chip-specific groups where each array chip has its own set of select gate lines (e.g., first select gate lines on first array chip, second select gate lines on second array chip). This segmentation ensures that select gate lines on different chips operate in electrically isolated environments, reducing mutual interference while allowing shared bit lines and word lines to provide efficient connectivity across chips.
Solution Approach 2:
Different regions of the device exhibit different electrical characteristics optimized for their specific functions. Array chip regions are designed with local electrical isolation for select gate lines to minimize interference, while circuit chip regions provide shared connectivity pathways for bit lines and word lines. This local quality differentiation allows simultaneous optimization of both electrical connectivity and interference reduction.
3Object-affected harmful factors
If select gate lines are made independent on each array chip, then interference is reduced, but device complexity increases
Solution Approach 1:
The device transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. By stacking array chips vertically in the third direction with circuit chips in between, the patent achieves electrical isolation of select gate lines through the vertical dimension rather than requiring complex lateral routing. This dimensional transition simplifies the overall device structure while maintaining independent select gate line operation on each chip.
Solution Approach 2:
Circuit chips serve multiple functions: they provide electrical connections between array chips via shared bit lines and word lines, they isolate select gate lines electrically, and they enable scalable stacking of multiple array chips. This multi-functionality reduces overall device complexity by consolidating multiple roles into single components rather than requiring separate structures for each function.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a first memory cell array, a second memory cell array, and a row decoder. The first memory cell array includes a first select transistor, a first memory cell, a second select transistor, a first word line, a first select gate line, and a second select gate line. The second memory cell array includes, a third select transistor, a second memory cell, a fourth select transistor, a second word line, a third select gate line, a fourth select gate line. The first word line and the second word line are commonly coupled to the row decoder. The first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder.