3D Stacked Memory Isolation of Defective Cell Layers
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Solution Overview
Problem
In three dimensionally stacked NAND flash memory devices, if the number of defective blocks in one or more memory cell layers exceeds a predetermined threshold, the entire chip is identified as defective, leading to reduced yield and capacity, even if other layers are normal, due to conventional inspection methods that do not account for the distribution of defective blocks across layers.
Innovation Solution
The implementation of a stacked memory cell array with a layer quality information storing circuit and an address converting circuit that logically and physically isolates defective memory cell layers, allowing normal layers to be used as a memory device with reduced capacity by address conversion and physical isolation, thereby preventing the entire chip from being identified as defective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inspection methods are used to identify defective chips, then the entire chip is identified as defective when the number of defective blocks in one or more memory cell layers exceeds a predetermined threshold, but this leads to reduced yield and capacity even when other layers are normal
Solution Approach 1:
The invention segments the memory device into multiple independent memory cell layers, allowing individual layer inspection and quality assessment. Each layer can be independently evaluated for defective blocks, and the overall chip quality is determined by the proportion of defective layers rather than requiring all layers to be perfect. This segmentation enables selective usage of healthy layers while isolating defective ones.
Solution Approach 2:
The invention applies local quality assessment by evaluating each memory cell layer individually for the presence and number of defective blocks. Instead of treating the entire chip as a single unit, the inspection method assesses the quality of each layer separately, allowing chips with some defective layers to still be utilized if the majority of layers are functional. This local quality approach enables capacity reduction rather than complete chip rejection.
2Reliability
If the entire chip is rejected when any layer has defective blocks, then chip reliability is maintained, but the usable capacity of the chip is significantly reduced
Solution Approach 1:
The memory device is divided into multiple independently inspectable memory cell layers. Each layer is evaluated separately for defective blocks, and the inspection results are aggregated to determine the overall chip quality. This segmentation allows the system to identify and isolate defective layers while preserving functional layers for data storage operations.
Solution Approach 2:
The invention applies partial action by accepting and utilizing only the functional portions of the chip (healthy memory cell layers) while discarding or isolating the defective portions. Instead of rejecting the entire chip when some layers are defective, the method performs partial inspection and utilization, allowing the device to operate with reduced capacity proportional to the number of functional layers.
Data Source
AI summary
There is provided a semiconductor memory device having a plurality of memory cell layers which can be used even if part of the memory cell layers is determined as defective. The semiconductor memory device includes a stacked memory cell array having a laminated plurality of memory cell layers, each of which has a plurality of blocks; a layer quality information storing circuit (10) which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify a memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and address converting circuit (11) in which if an externally input address input from outside corresponds to the block in the defective memory cell layer, the externally input address is address-converted so as to correspond to the block of the normal memory cell layer.