Stacked Memory Chips with Jumper Interconnects for Routability
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Solution Overview
Problem
The increasing demand for higher performing portable electronic devices with multiple functions, such as mobile phones and multimedia players, requires a semiconductor package with improved routability and increased memory capacity, which is challenging due to complex wiring structures and the need for multiple semiconductor chips with different memory capacities.
Innovation Solution
A semiconductor package design featuring a first and second semiconductor package with memory chips of different capacities, where the first package includes memory chips with twice the capacity of the second, and jumper chips for electrical connections, improving routability and package properties by simplifying interconnection structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips with different capacities are integrated in a multi-chip package structure, then memory capacity is increased, but wiring structure becomes complex and routability decreases
Solution Approach 1:
The package is divided into multiple semiconductor packages, each containing memory chips with different capacities. This segmentation allows independent wiring designs for each package, reducing overall wiring complexity while maintaining high memory capacity through the combination of multiple packages.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration with multiple packages positioned at different heights. This vertical stacking reduces the horizontal wiring complexity and improves routability by utilizing the vertical dimension for interconnections.
2Quantity of substance
If multiple memory chips are stacked in a package, then memory capacity is increased, but vertical thickness increases
Solution Approach 1:
Multiple semiconductor packages are nested vertically, with smaller packages positioned on top of larger ones. This nesting arrangement optimizes the use of vertical space and reduces the overall vertical thickness compared to a simple stacked configuration, while still achieving high memory capacity through the combined storage of multiple packages.
3Length of stationary object
If memory chips are closely arranged to reduce vertical thickness, then package size is reduced, but signal transmission paths increase and data latency worsens
Solution Approach 1:
Jumper chips are introduced as intermediary elements between memory chips of different capacities. These jumper chips provide optimized signal transmission paths that reduce data latency, allowing closely arranged memory chips to maintain fast communication despite their compact vertical configuration.
Data Source
AI summary
According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package.