Stacked Semiconductor Memory Layers for Density Without Excess Complexity
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in optimizing the structure and manufacturing process to enhance data storage capacity and efficiency, particularly in the design of gate insulating layers and conductive layers, which affect the performance and reliability of memory cells.
Innovation Solution
The semiconductor memory device incorporates a novel configuration with multiple conductive layers and semiconductor layers separated by insulating layers, including a floating gate and electric charge accumulating layers, optimized through a specific manufacturing process involving Chemical Vapor Deposition (CVD) and Reactive Ion Etching (RIE) to form precise conductive and insulating structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conductive layers and semiconductor layers are stacked to increase data storage capacity, then storage density is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple string units, each containing separate first and second semiconductor layers with independent conductive layers. This segmentation allows parallel data storage operations across different string units, increasing storage capacity while managing complexity through modular organization
Solution Approach 2:
The patent transitions from planar memory structures to three-dimensional stacked architectures with conductive layers arranged in vertical directions intersecting the substrate. Multiple semiconductor layers are positioned at different heights, enabling increased storage density by utilizing the vertical dimension rather than only horizontal expansion
2Manufacturing precision
If precise conductive and insulating structures are formed through CVD and RIE processes, then manufacturing precision is improved, but manufacturing difficulty increases
Solution Approach 1:
sacrificial layers are formed in advance before the final conductive layers are deposited. These sacrificial layers serve as temporary structures that guide the formation of precise conductive and insulating layers through CVD and RIE processes, enabling high manufacturing precision while simplifying the overall manufacturing sequence
Solution Approach 2:
The patent employs controlled variations in deposition and etching parameters during CVD and RIE processes to achieve precise thickness control and dimensional accuracy of conductive and insulating layers. By optimizing parameters such as temperature, pressure, and gas flow rates, high manufacturing precision is achieved while maintaining process feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data storage capacity and efficiency by improving the integrity and functionality of memory cells, leading to improved performance and reliability in semiconductor memory devices.
Implementation Method 1
optimized through a specific manufacturing process involving Chemical Vapor Deposition (CVD)
Implementation Method 2
optimized through a specific manufacturing process involving Chemical Vapor Deposition (CVD) and Reactive Ion Etching (RIE)
Data Source
AI summary
A semiconductor memory device comprises: first to third layers; first and second semiconductor layers opposed to the first to third layers; and first to third electrodes connected to the first to third layers. The first layer includes: a first conductive layer opposed to the first semiconductor layer and connected to the first electrode; a second conductive layer opposed to the second semiconductor layer; and an intermediate layer continuously formed in a region between the second electrode and the third electrode without being electrically connected to the first conductive layer or the second conductive layer. Each of the second layer and the third layer includes a third conductive layer that is continuously formed in a region between the first semiconductor layer and the second semiconductor layer and opposed to the first and second semiconductor layers.