Stacked Memory Device with Local Processors and TSVs
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Solution Overview
Problem
Current memory devices face performance bottlenecks due to high memory bandwidth and latency requirements, which are exacerbated by the need for separate systems and inter-device communication, leading to increased latency and power consumption.
Innovation Solution
A stacked memory device architecture that includes a logic semiconductor die with a global processor and multiple memory semiconductor dies with local processors, connected via through-silicon vias, allowing for distributed data processing to reduce latency and power consumption by performing global and local sub-processes within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are implemented as separate systems with inter-device communication, then memory capacity can be increased, but bandwidth and latency penalties occur twice for each access
Solution Approach 1:
The patent merges the memory system and processor system into a single stacked device, eliminating the need for external inter-device communication. The processor die and memory dies are vertically integrated with direct electrical connections through TSVs, consolidating what were previously separate systems into one unified device that processes and stores data internally without external bandwidth penalties.
Solution Approach 2:
The patent transitions from a planar, separate-system architecture to a three-dimensional stacked architecture. By stacking the processor die and multiple memory dies vertically and connecting them through TSVs, the invention utilizes the vertical dimension to reduce communication distance and eliminate external interface overhead, thereby reducing latency while maintaining high capacity.
2Quantity of substance
If memory devices are implemented as separate systems, then memory capacity can be increased, but inter-device bandwidth penalties occur
Solution Approach 1:
The patent merges the memory system and processor system into a single stacked device, eliminating the need for external inter-device communication. The processor die and memory dies are vertically integrated with direct electrical connections through TSVs, consolidating what were previously separate systems into one unified device that processes and stores data internally without external bandwidth penalties.
3Adaptability or versatility
If data processing is performed externally, then system flexibility is maintained, but power consumption increases due to external communication
Solution Approach 1:
The patent merges the memory system and processor system into a single stacked device, eliminating the need for external inter-device communication. The processor die and memory dies are vertically integrated with direct electrical connections through TSVs, consolidating what were previously separate systems into one unified device that processes and stores data internally without external bandwidth penalties.
Data Source
AI summary
A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.