Stacked Memory-on-Logic Chip Layout for Compact High-Capacity Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges in improving reliability and durability while maintaining cost-effectiveness, particularly in integrating semiconductor chips with high memory capacity in a reduced horizontal size.
Innovation Solution
A semiconductor chip design featuring a logic die with memory dies stacked on top, separated by a mold layer, and connected via mold vias, utilizing distinct materials for the mold and interlayer insulating layers to enhance integration and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are arranged side by side on the logic die to increase memory capacity, then the memory capacity is improved, but the horizontal size of the semiconductor chip increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of memory dies to a three-dimensional stacked configuration. Multiple memory dies are vertically stacked above the logic die, utilizing the vertical dimension (Z-axis) to increase memory capacity without expanding the horizontal footprint. This dimensional transition directly resolves the contradiction by enabling higher density integration while maintaining a compact chip footprint.
2Adaptability or versatility
If multiple memory dies are integrated on a single logic die to increase functionality, then the integration level is improved, but the device complexity increases
Solution Approach 1:
The patent divides the semiconductor chip into distinct functional segments: a logic die and multiple memory dies. Each die is independently designed, manufactured, and tested as a separate unit, then bonded together through standardized interconnect structures. This segmentation allows for specialized optimization of each component while simplifying the overall integration process through modular assembly, thereby increasing functionality without proportionally increasing complexity.
Solution Approach 2:
The patent introduces a mold layer as an intermediary component between the logic die and memory dies, and between adjacent memory dies. This mold layer serves multiple functions: providing mechanical support, enabling precise alignment, facilitating thermal management, and serving as a mounting substrate for bonding connections. The intermediary mold layer simplifies the integration of multiple dies by providing a standardized interface and structural framework.
3Ease of manufacture
If conventional bonding methods are used to connect memory dies to logic die, then the manufacturing process is simple, but the reliability and durability are insufficient
Solution Approach 1:
The patent employs composite material structures in the bonding interfaces between dies. The mold layer comprises composite materials combining organic resin matrices with inorganic fillers, providing enhanced mechanical strength, thermal conductivity, and adhesion properties. This composite approach improves the reliability and durability of die-to-die and die-to-substrate connections while maintaining compatibility with existing manufacturing processes.
Data Source
AI summary
Provided are a semiconductor chip, a semiconductor package including the same, and a method for manufacturing the same. This semiconductor chip includes a first logic die, first memory dies arranged side by side in a first direction on the first logic die, and a first mold layer between the first memory dies. The first memory dies and the first mold layer are in contact with an upper surface of the first logic die, each of the first memory dies includes first memory bank regions arranged side by side in a second direction intersecting the first direction, and the first logic die includes first core regions overlapping the first memory bank regions, respectively, in a third direction that is perpendicular to the first and second directions.