3D Stacked Semiconductor Memory-Logic Structure for Faster PIM
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Solution Overview
Problem
The von Neumann structure's memory and arithmetic devices require significant data transfer time for large computations, leading to reduced computation speed, and memory devices with processing-in-memory (PIM) structures are physically larger due to computation circuits.
Innovation Solution
A semiconductor device with a stacked cell structure and logic structures connected by tapered through vias, allowing for reduced size and simplified manufacturing through wafer thinning and hybrid copper bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory device with PIM structure is used to perform computations within the memory device, then computation speed is improved, but the device size increases due to inclusion of computation circuits and cache memory
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where memory cells and logic circuits are arranged in vertical layers. Multiple substrates are bonded together with through-vias connecting different levels, enabling spatial separation of memory and logic functions while maintaining compact footprint. This vertical stacking allows computation circuits to be integrated with memory cells without increasing the lateral device area.
2Device complexity
If data transfer between separate memory device and arithmetic device is required in von Neumann structure, then device complexity is reduced, but computation speed decreases due to data transfer time
Solution Approach 1:
The patent merges memory cells and logic circuits into a single integrated device structure. Memory cells are formed on first substrate while logic circuits are formed on second substrate, which is then bonded to the first substrate. Through-vias establish direct electrical connections between memory and logic components, eliminating the need for external data transfer between separate devices while maintaining the functional separation of memory and arithmetic operations.
3Area of stationary object
If wafer thinning process is performed to reduce substrate thickness, then device size is reduced, but manufacturing precision requirements increase to expose insulating patterns accurately
Solution Approach 1:
The insulating patterns are formed on the substrate surfaces before the wafer thinning process. By preparing these patterns in advance at a thicker substrate stage, the subsequent thinning operation can be performed with more controlled precision, as the patterns serve as pre-established reference features that guide the thinning process to the correct depth without requiring extremely high precision during the thinning operation itself.
Data Source
AI summary
The present disclosure relates to a semiconductor device and a manufacturing method therefor. A semiconductor device includes a cell structure including a first substrate and a plurality of memory cells on the first substrate; a first logic structure on the cell structure and including a second substrate and a first logic circuit on the second substrate; a second logic structure on the first logic structure and including a third substrate and a second logic circuit on the third substrate; and a through via extending through a first insulating pattern in the second substrate and a second insulating pattern in the third substrate.