3D Stacked Memory Sparing With Logic-Die Remapping
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Solution Overview
Problem
The yield of stacked memory systems, particularly 3D stacked memory systems, is adversely affected due to compounded non-perfect yields of semiconductor wafers, leading to reduced performance and increased manufacturing costs, as failed components in the array die stack cannot be effectively replaced.
Innovation Solution
Incorporating spare arrays or dies within the array die stack and using logic circuitry to remap accesses to failed components to spare components, thereby supporting sparing techniques that improve yield and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spare arrays or dies are incorporated within the array die stack, then the yield and performance of 3D stacked memory systems are improved by allowing failed components to be replaced, but the device complexity increases due to additional components and remapping logic
Solution Approach 1:
Spare arrays or dies are pre-included within the array die stack during manufacturing, before any failures occur. The logic circuitry is also pre-configured to perform remapping operations. When a failure is detected, the system immediately switches to using the spare components through the pre-configured remapping logic, eliminating the need for post-failure redesign or complex repair processes.
Solution Approach 2:
Logic circuitry acts as an intermediary between the host system and the memory arrays. This intermediary remapping logic detects failures in memory components and automatically redirects access requests to spare arrays or dies, hiding the complexity of failure replacement from the host system while enabling reliable operation despite component failures.
2Reliability
If spare arrays or dies are incorporated within the array die stack, then the yield and performance of 3D stacked memory systems are improved, but the manufacturing costs and time-to-market increase
Solution Approach 1:
Spare components are included in the manufacturing process from the outset, allowing defects to be detected and addressed during factory testing rather than after delivery. This preliminary inclusion enables batch processing of spares with the main array dies, consolidating manufacturing operations and avoiding the need for separate, time-consuming repair operations after products reach customers.
3Device complexity
If failed components in the array die stack cannot be effectively replaced, then the device complexity remains low, but the yield and performance are adversely affected
Solution Approach 1:
Spare arrays or dies are nested within the existing array die stack structure, utilizing the same physical and logical space as the operational memory components. The logic circuitry is integrated into the existing die architecture, allowing failure replacement functionality to be embedded within the standard memory access paths without requiring separate external replacement mechanisms.
Data Source
AI summary
Methods, systems, and devices for sparing techniques in stacked memory architectures are described. A memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.