Stacked Silicon and Metal Oxide Memory Circuit for Low Leakage
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing power consumption and leakage current due to variations in threshold voltages of silicon transistors with miniaturization, especially in nonvolatile memory devices like NOSRAM, where Si transistors have high on-state current and increased leakage current with higher integration.
Innovation Solution
A semiconductor device is designed with a stacked structure of silicon transistors and metal oxide transistors, utilizing back gate electrodes and insulating layers to control threshold voltages and reduce leakage current, where silicon transistors are integrated with buried oxide layers and metal oxide transistors are stacked above, leveraging the low off-state current of metal oxide transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon transistors are miniaturized to increase integration density, then productivity and device density improve, but threshold voltage variations increase and leakage current worsens
Solution Approach 1:
The patent introduces a back gate electrode that applies electric field from a different dimension (vertical field through the substrate) to control the threshold voltage of silicon transistors. This allows independent control of threshold voltage without changing the horizontal transistor dimensions, thus maintaining high integration density while achieving stable threshold voltage through vertical field effect.
2Power
If silicon transistors are used for high on-state current, then power delivery capability improves, but leakage current and standby power consumption worsen
Solution Approach 1:
The patent merges silicon transistors and metal oxide transistors into a single integrated circuit, allowing each transistor type to perform its optimal function. Silicon transistors provide high on-state current where needed, while metal oxide transistors provide low leakage current in other positions, achieving overall low power consumption without sacrificing power delivery capability.
Solution Approach 2:
The patent changes the material parameter (semiconductor type) of specific transistors from silicon to metal oxide based on their functional requirements. Metal oxide transistors are used where low leakage is critical, while silicon transistors are used where high on-state current is needed, optimizing the overall circuit performance.
3Use of energy by moving object
If signal voltages are reduced to lower power consumption during data reading, then energy efficiency improves, but the ability to drive silicon transistors with varying threshold voltages worsens
Solution Approach 1:
The patent applies preliminary action by using the back gate electrode to pre-adjust the threshold voltage of silicon transistors before data reading operations. This ensures that transistors are optimally biased for low-voltage operation, enabling reduced signal voltages during reading without compromising the ability to properly drive the transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves reduced power consumption and leakage current, maintaining stable operation even in high-temperature environments, with the metal oxide transistors providing low off-state current and silicon transistors controlling threshold voltages without increasing circuit area.
Implementation Method 1
A transistor including a metal oxide semiconductor in a channel formation region has extremely low off-state current
Implementation Method 2
The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a memory circuit including a first transistor and a second transistor. The first transistor is formed on a silicon substrate. The second transistor is formed in a layer above a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode with a first channel formation region interposed therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate. The second transistor includes a second channel formation region. The second channel formation region includes a metal oxide.