Stacked Oxide-Silicon Memory Circuit for Low-Leakage Data Retention
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low off-state current, high reliability, low power consumption, reduced manufacturing costs, and smaller size while maintaining data integrity and efficiency.
Innovation Solution
A semiconductor device structure incorporating a silicon substrate with stacked transistor layers, including both silicon and metal oxide transistors, utilizing a correction circuit to manage threshold voltage and bit lines in a perpendicular configuration, facilitating low off-state current and efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional Si transistors are used in stacked memory structures, then manufacturing process compatibility is maintained, but off-state current remains high leading to high power consumption
Solution Approach 1:
The invention divides the transistor structure into distinct material layers: a silicon-based semiconductor layer for the channel and a metal oxide semiconductor layer for the gate electrode. This segmentation allows each layer to contribute its optimal properties - silicon provides good carrier mobility while metal oxide provides high breakdown voltage and low off-state current, thereby reducing power consumption while maintaining data retention capability
Solution Approach 2:
The invention employs composite materials by combining silicon-based semiconductor with metal oxide semiconductor in a stacked transistor structure. The silicon layer serves as the channel formation region while the metal oxide layer forms the gate electrode, creating a heterostructure that leverages the complementary electrical characteristics of both materials to achieve low power consumption and high reliability simultaneously
2Reliability
If metal oxide semiconductor is used in channel formation region, then off-state current is reduced, but manufacturing process integration becomes complex
Solution Approach 1:
The invention transitions from planar integration to vertical stacking by forming the metal oxide semiconductor layer over the silicon-based semiconductor layer in a stacked configuration. This vertical arrangement in the thickness direction allows both material types to be integrated without requiring complex lateral process modifications, maintaining compatibility with existing CMOS manufacturing processes while achieving low off-state current characteristics
Solution Approach 2:
The stacked transistor structure serves multiple functions: the silicon-based layer provides the channel with good carrier mobility, the metal oxide layer provides the gate electrode with high breakdown voltage, and together they enable low off-state current while remaining compatible with standard semiconductor manufacturing processes through vertical stacking
3Productivity
If stacked transistor layers are implemented, then device density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The invention merges the formation of multiple transistor layers into a unified stacked structure where the metal oxide semiconductor layer is formed directly over the silicon-based semiconductor layer. This combined structure reduces the need for separate alignment processes for multiple planar layers, as the vertical stacking can be achieved through conformal deposition techniques that maintain precision while increasing device density
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.