Stacked Memory Deck Interconnect Layout for Misalignment Tolerance
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Solution Overview
Problem
Existing technologies face challenges in coupling circuitry from upper decks with that of lower decks in stacked integrated circuitry, particularly due to misalignment issues.
Innovation Solution
The implementation of conductive extensions from wordlines and/or digit-lines of one memory deck crossing conductive lines of another deck, allowing for interconnects to be formed even with misalignment, and utilizing vertical interconnects to couple these extensions with conductive lines on the base deck.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertically-stacked decks are used to increase integration, then integration capability is improved, but misalignment between decks occurs causing coupling difficulties
Solution Approach 1:
The patent divides the interconnect structure into multiple segments: conductive lines on the base deck, conductive extensions on the memory deck, and vertical interconnects coupling them. This segmentation allows independent optimization of each component and facilitates misalignment compensation through the overlapping configuration of extensions and lines.
Solution Approach 2:
The patent transitions from two-dimensional planar interconnects to three-dimensional vertically-stacked interconnects. Conductive extensions protrude from the memory deck in a direction substantially perpendicular to the base deck, creating vertical coupling paths that enable integration across multiple stacked decks while accommodating lateral misalignment.
2Reliability
If conductive extensions protrude from memory deck to couple with base deck, then coupling effectiveness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the conductive extension structure with the existing memory cell array fabrication process. The extensions are formed using the same semiconductor processing steps as the memory cells themselves, integrating the interconnect formation into the standard manufacturing flow and reducing overall process complexity.
Solution Approach 2:
The conductive extensions act as intermediary elements that bridge the memory deck and base deck. These extensions protrude from the memory deck to overlap with conductive lines on the base deck, creating reliable coupling paths while allowing for misalignment compensation through the overlapping configuration.
3Reliability
If vertical interconnects are used to couple decks, then interconnection reliability is improved, but alignment tolerance requirements increase
Solution Approach 1:
The patent performs preliminary alignment compensation by designing conductive extensions with specific geometries and positions that anticipate and compensate for expected misalignment. The extensions are configured to overlap with conductive lines on the base deck in a manner that ensures coupling even when perfect alignment is not achieved.
Solution Approach 2:
The patent changes the geometric parameters of the conductive extensions, such as their length, width, and protrusion distance, to optimize the overlap region with base deck conductive lines. By adjusting these parameters, the design achieves reliable coupling with relaxed alignment tolerance requirements.
Data Source
AI summary
Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.