Stacked Memory Module Packaging Without a Package Substrate
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Solution Overview
Problem
Conventional semiconductor modules with stacked memory configurations face increased manufacturing costs due to complex I/O connection structures and additional process steps, such as build-up wiring and through vias, which hinder cost-effective production of modules with multiple chips.
Innovation Solution
A method and module design utilizing fan-out wafer level packaging (FOWLP) technology to stack memory chips in a bump-less manner, eliminating the need for a package substrate, and incorporating external through electrodes and redistribution layers to facilitate cost-effective manufacturing of thin, high-capacity modules with reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bridge connection or interposer structures are used for stacking memory chips, then connection reliability is improved, but manufacturing cost increases due to additional I/O connection structures and process steps
Solution Approach 1:
The patent extracts and eliminates the package substrate from the conventional stacked memory structure. By directly bonding memory chips to each other without requiring a separate package substrate, the invention removes the source of complex I/O connection structures and through vias, thereby reducing manufacturing cost while maintaining connection reliability through direct chip-to-chip bonding
Solution Approach 2:
The patent merges the package substrate function directly into the memory chip structure itself. The lowest memory chip serves as the base layer, eliminating the need for a separate package substrate. This merging reduces the number of components and interconnection structures required, simplifying the overall manufacturing process while maintaining structural integrity
2Reliability
If build-up wiring and through vias are formed on molding material for I/O connections, then electrical connectivity is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The patent performs preliminary wiring formation on the memory chips themselves before stacking. The input/output wiring layers are formed on the memory chip surfaces during chip fabrication, eliminating the need for subsequent build-up wiring and through via formation on the package substrate after stacking. This preliminary action reduces the number of process steps while ensuring electrical connectivity is established before assembly
3Quantity of substance
If multiple memory chips are stacked with conventional packaging, then memory capacity is increased, but module thickness increases due to package substrate and molding material
Solution Approach 1:
The patent extracts and removes the package substrate and excessive molding material from the conventional stacked memory structure. By eliminating these thick layers and using direct chip bonding, the invention achieves high memory capacity through stacking while minimizing the overall module thickness, creating a thin-profile high-capacity memory device
Data Source
AI summary
A method for manufacturing a module including a predetermined number of multilayered memories includes a multilayered wafer formation step of forming a multilayered wafer by bumpless stacking of a plurality of memory wafers; a singulating step of singulating the multilayered wafer into multilayered memories; a rearranging step of rearranging the plurality of multilayered memories in a predetermined shape; a molding step of molding the rearranged multilayered memories; a wiring formation step of forming external wiring in the multilayered memories; and a separation step of separating into a memory module including a predetermined number of molded multilayered memories.