Stacked Memory Offset Interconnects for Scalable Bandwidth
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Solution Overview
Problem
Conventional 3D stacked memory devices are limited in bandwidth, requiring significant electrical loading and excessive power consumption due to tied data interface pins, which restricts the maximum data rate and does not allow bandwidth to scale with the addition of memory layers.
Innovation Solution
The implementation of offset interconnects between memory die layers in a stacked memory device, where each die layer drives multiple channels and uses staggered or wrap-around routing to re-route signal paths, reducing electrical loading and increasing bandwidth with each additional layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data interface pins are tied together in conventional 3D stacked memory, then memory density increases with additional layers, but bandwidth remains limited and power consumption increases
Solution Approach 1:
The patent segments the data interface pins into multiple independent channels instead of tying them together. Each memory die layer can drive multiple channels independently, allowing bandwidth to scale with the number of layers while maintaining manageable electrical loading on each pin.
Solution Approach 2:
The patent introduces offset interconnects that route signals through multiple die layers in a staggered pattern, effectively utilizing the vertical dimension of the stacked memory architecture to expand bandwidth capacity beyond what single-layer interfaces can provide.
2Quantity of substance
If data interface pins are tied together in conventional 3D stacked memory, then memory density increases with additional layers, but electrical loading increases and power consumption increases
Solution Approach 1:
By dividing the interface into multiple channels and having each pin drive only its assigned channel, the electrical loading on individual pins is reduced. This segmentation allows higher memory density without proportionally increasing power consumption, as each pin operates within manageable electrical constraints.
Solution Approach 2:
The patent changes the electrical loading parameter by offsetting interconnect routes between layers, ensuring that signals from multiple layers do not simultaneously load the same pins. This parameter change reduces peak current draw and power consumption while maintaining high memory density.
3Quantity of substance
If data interface pins are tied together in conventional 3D stacked memory, then memory density increases with additional layers, but maximum data rate decreases
Solution Approach 1:
Segmenting the interface into multiple channels allows parallel data transmission, increasing the maximum data rate. Each channel operates independently at optimized speeds, and the aggregate bandwidth scales with the number of active channels and layers.
Solution Approach 2:
The offset interconnect routing utilizes the vertical stacking dimension to create multiple parallel signal paths through different layers. This dimensional approach enables higher data rates by distributing traffic across multiple spatial paths rather than congesting single-layer interfaces.
4Device complexity
If conventional tied interface design is used, then device structure is simple, but bandwidth does not scale with additional memory layers
Solution Approach 1:
The segmented channel structure provides a scalable framework where bandwidth capacity can be increased by activating additional channels and layers without redesigning the fundamental interface architecture. This segmentation enables progressive bandwidth scaling while maintaining reasonable device complexity.
Solution Approach 2:
The offset interconnect design creates a universal interface structure that can support varying numbers of memory layers and channels. The same basic architecture scales from low-bandwidth to high-bandwidth configurations, providing bandwidth scalability without requiring fundamentally different designs for different capacity levels.
Data Source
AI summary
A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.