Vertically Stacked Memory Arrays with Orthogonal Access Lines
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Solution Overview
Problem
Current memory technologies face challenges in achieving smaller and denser integrated circuits due to the complexity of memory cell structures, particularly in transitioning between resistive states in nonvolatile memory cells, such as RRAM and PMCs, which require efficient control of charge carriers like ions to maintain data retention without refresh.
Innovation Solution
The development of arrays of vertically stacked tiers of memory cells with programmable materials, such as chalcogenide or metal oxide-based materials, between conductive electrodes, where access and sense lines are orthogonally arranged, and select transistors are used to control the programmable material's resistive states, enabling efficient data storage and retrieval by manipulating charge density distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell structures are simplified to reduce size, then device density increases, but data retention capability without refresh deteriorates
Solution Approach 1:
The patent changes the fundamental operating parameter of the memory cell from volatile (requiring refresh) to non-volatile (retaining data without refresh) by using programmable materials that can maintain resistive states. This allows simplified memory cell structures to achieve both high density and data retention capability simultaneously.
Solution Approach 2:
The patent employs composite material structures including programmable materials (such as chalcogenide or metal oxide-based materials) positioned between conductive electrodes. These composite structures enable the memory cell to achieve non-volatile operation while maintaining a simplified, space-efficient design that increases device density.
2Quantity of substance
If vertically stacked tiers are used to increase density, then device complexity increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangements to vertically stacked (3D) tiers, thereby increasing memory array density by utilizing the vertical dimension. This dimensional change allows higher density while the self-aligned fabrication processes mitigate the increase in manufacturing complexity.
Solution Approach 2:
The patent divides the memory array into multiple vertically stacked tiers, with each tier containing memory cells formed by intersections of access lines and sense lines. This segmentation into discrete, repeatable units simplifies the manufacturing process for each individual tier while achieving high overall density through vertical stacking.
3Quantity of substance
If access and sense lines are orthogonally arranged in vertically stacked tiers, then data storage capacity increases, but device complexity increases
Solution Approach 1:
The patent arranges access lines and sense lines in orthogonal configurations across vertically stacked tiers, utilizing three-dimensional spatial arrangement to increase data storage capacity. This orthogonal 3D arrangement allows multiple memory cells to be formed at line intersections across different vertical levels, dramatically increasing storage capacity while the systematic pattern reduces control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-density memory arrays with efficient data storage and retrieval capabilities, maintaining resistive states without the need for frequent refresh, thereby enhancing the performance and durability of nonvolatile memory cells.
Implementation Method 1
Some programmable materials may contain mobile charge carriers larger than electrons and holes, for example ions in some example applications. Regardless, the programmable materials may be converted from one memory state to another by moving the mobile charge carriers to alter a distribution of charge density within the programmable materials.
Implementation Method 2
A suitable voltage applied across the electrodes generates current conductive super-ionic clusters or filaments. Such result from ion transport through the ion conductive material which grows the clusters/filaments from one of the electrodes (the cathode), through the ion conductive material, and toward the other electrode (the anode).
Data Source
AI summary
An array of vertically stacked tiers of memory cells includes horizontally oriented access lines within individual tiers of memory cells and horizontally oriented global sense lines elevationally outward of the tiers. Select transistors are elevationally inward of the tiers. Pairs of local first and second vertical lines extends through the tiers. One vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects including methods, are disclosed.