Stacked Memory Cell Layout With Oxide TFTs for Data Retention
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high storage capacity per unit area and efficient data storage due to limitations in memory cell stacking and data retention.
Innovation Solution
A semiconductor device with a novel structure featuring stacked memory cells, including transistors and capacitors with oxide semiconductors, where the channel length direction of one transistor is perpendicular to the channel length direction of another, allowing for increased storage capacity and improved data retention through reduced off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional stacking of memory cells vertically over the substrate, transitioning from planar two-dimensional arrangement to three-dimensional configuration. Multiple memory cells are stacked in the vertical direction with each cell containing transistors and capacitors arranged in different orientations, enabling increased storage capacity per unit area while maintaining manageable complexity through systematic vertical integration
Solution Approach 2:
The memory device is divided into multiple discrete memory cells stacked vertically, with each cell being a separate functional unit containing its own transistors and capacitors. This segmentation allows independent operation and simplification of individual cell design while achieving high overall storage capacity through the stacked configuration
2Reliability
If oxide semiconductors are used to reduce off-state current, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs oxide semiconductor materials as the semiconductor layer in the transistor structure, utilizing the unique properties of oxide semiconductors to achieve extremely low off-state current. This material selection improves data retention by ensuring stable charge storage in the capacitor while the oxide semiconductor provides the necessary electrical characteristics for reliable memory operation
3Quantity of substance
If transistors with perpendicular channel length directions are used, then storage capacity per unit area is improved, but device complexity increases
Solution Approach 1:
The patent utilizes three-dimensional spatial arrangement where transistors in different memory cells have channel length directions oriented perpendicularly to each other. This perpendicular orientation allows efficient packing of multiple memory cells in the vertical stack, maximizing storage capacity per unit area by utilizing vertical space effectively while maintaining clear directional separation of current flow paths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a significant increase in storage capacity per unit area and enhances data retention by utilizing oxide semiconductors with extremely low off-state current, reducing the need for high electrical fields and eliminating limitations on the number of write cycles, thus improving the reliability and operation speed of semiconductor devices.
Implementation Method 1
The second transistor and the fourth transistor include an oxide semiconductor. A channel length direction of the first transistor and the third transistor is substantially perpendicular to a channel length direction of the second transistor and the fourth transistor.
Data Source
AI summary
The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.