Stacked Semiconductor Package Layout for Higher Memory Density
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Solution Overview
Problem
The demand for increased data storage capacity in semiconductor memory devices is limited by their physical size and heat dissipation requirements, making it challenging to enhance storage without expanding the device's dimensions.
Innovation Solution
A combined semiconductor device package is designed, featuring two semiconductor chips housed in separate enclosures with solder balls and conductive pads that allow for electrical communication and stacking within a printed circuit board, effectively increasing storage capacity without increasing the device's size by utilizing existing form factor dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor packages are placed on a substrate to increase storage capacity, then the total storage capacity increases, but the physical area occupied increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where multiple packages occupy separate areas on a substrate to a three-dimensional stacked configuration where packages are vertically arranged. The first and second semiconductor packages are positioned at different heights (first vertical position and second vertical position respectively), allowing multiple storage units to coexist within the same horizontal footprint, thereby dramatically increasing storage capacity without expanding the device's planar dimensions
Solution Approach 2:
The patent implements a nested structure where the second semiconductor package is positioned within the vertical space above the first semiconductor package. The packages are arranged such that they occupy overlapping horizontal projections but different vertical levels, creating a space-efficient configuration where one package is effectively nested within the vertical envelope of another, maximizing storage density within the available three-dimensional space
2Quantity of substance
If the physical size of semiconductor devices is increased to accommodate more storage, then storage capacity increases, but the device dimensions exceed existing form factor requirements
Solution Approach 1:
The invention exploits the vertical dimension to increase storage capacity while maintaining compliance with existing form factor requirements. By stacking packages vertically rather than expanding horizontally, the device achieves higher storage capacity within the same lateral dimensions, ensuring compatibility with standard substrate and housing form factors without requiring larger device footprints
3Quantity of substance
If multiple semiconductor packages are stacked vertically, then storage capacity increases within the same footprint, but heat dissipation becomes more challenging
Solution Approach 1:
The patent introduces thermal management structures as intermediary elements between the stacked semiconductor packages. These intermediaries facilitate heat transfer from the upper package to the lower package or to dedicated heat sinks, enabling effective thermal management in the vertical stacking configuration and preventing heat accumulation that would otherwise result from reduced air circulation and increased thermal resistance in the stacked arrangement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables enhanced data storage capacity by stacking semiconductor chips within the existing form factor, reducing signal latency and maintaining compatibility with existing PCB dimensions, thus addressing the limitations of physical size and heat dissipation.
Implementation Method 1
the first substrate including a first plurality of solder balls and a second plurality of solder balls, the first plurality of solder balls and the second plurality of solder balls each in electrical communication with the first semiconductor chip
Data Source
AI summary
A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package. The combined semiconductor device package may be used for packaging a memory device that allows for increased memory package without increasing the package form factor.