Stacked Memory Logic Die Packet Broadcaster for High Bandwidth Testing
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Solution Overview
Problem
Conventional memory devices, such as DRAM, struggle to keep up with increasing data bandwidth demands, leading to performance bottlenecks in computer systems, and existing testing systems are incompatible with new memory designs, requiring significant investment and time to adapt.
Innovation Solution
A high-capacity, high-bandwidth memory device architecture featuring stacked DRAM die connected via a wide bus, with a logic die that manages data serialization and deserialization, and a packet builder and broadcaster to enable testing with conventional equipment by reformating test signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory device bandwidth is increased using wider internal data buses, then data transfer speed is improved, but device complexity increases due to serialization and deserialization requirements
Solution Approach 1:
A serializer/deserializer interface circuit is introduced as an intermediary component between the wide internal data bus and the external data bus. This mediator handles the complex serialization and deserialization operations, allowing the memory device to achieve high bandwidth through wider internal buses while managing the complexity through a dedicated interface layer rather than distributing it throughout the entire device architecture.
2Speed
If new memory device designs are developed to increase bandwidth, then data transfer capability is improved, but compatibility with conventional test equipment is lost
Solution Approach 1:
The memory device incorporates a universal interface design that can operate in multiple modes. The device includes test mode circuitry that enables it to interface with both conventional test equipment and modern high-speed testing systems. This multi-functionality allows the high-bandwidth memory device to maintain backward compatibility with legacy testers while utilizing advanced testing capabilities when available.
3Ease of manufacture
If conventional test equipment is used to test new memory designs, then testing cost is reduced, but testing capability is insufficient for high bandwidth devices
Solution Approach 1:
The memory device incorporates dynamic test mode selection capabilities that allow it to adapt its interface behavior based on the capabilities of the connected test equipment. The device can dynamically switch between different testing protocols and interface modes, enabling conventional test equipment to effectively test high-bandwidth devices by adapting the testing approach rather than requiring upgrades to the test equipment itself.
Data Source
AI summary
A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.