3D Stacked Memory Cells With Shared Reduced-Pitch Bit Lines
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Solution Overview
Problem
Conventional semiconductor memory devices with stacked memory cells face challenges in increasing integration density and miniaturization, particularly in the alignment and connection of bit lines to memory units, which limits their performance and efficiency.
Innovation Solution
The semiconductor memory device employs a configuration where bit lines are aligned with a pitch less than that of memory units, with alternating connections to two bit lines per column group, allowing for increased page length and improved read/write speed without expanding circuit area, utilizing a U-shaped semiconductor layer as the channel body and optimizing the arrangement of select gate lines and sense amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit lines are aligned with the same pitch as memory units, then the alignment and connection are simplified, but the page length and read/write speed are limited
Solution Approach 1:
The patent introduces a new dimensional relationship between bit lines and memory units by aligning bit lines with a pitch less than that of memory units. This creates a multi-to-one mapping where multiple memory units can be accessed through fewer bit lines, effectively adding a dimensional layer to the connection topology that increases page length without proportionally increasing bit line count
Solution Approach 2:
The patent merges multiple memory units into column groups that share common bit lines. By combining the functionality of multiple individual connections into shared resources, the system achieves longer page lengths and improved read/write speed while controlling the number of physical bit lines required
2Productivity
If the circuit area is expanded to increase page length, then more bits can be read/written in parallel, but the device size increases
Solution Approach 1:
Instead of expanding circuit area horizontally to increase page length, the patent utilizes vertical stacking of memory units and implements a pitch-reduced bit line alignment. This dimensional reorganization allows multiple memory units to share bit lines, effectively increasing the number of bits that can be read/written in parallel without proportionally increasing the physical circuit area
Solution Approach 2:
The patent makes bit lines universal by having them serve multiple memory units through the reduced pitch alignment. Each bit line becomes a multi-functional resource that can interface with multiple memory units in different column groups, increasing the effective page length without requiring dedicated bit lines for each memory unit
Data Source
AI summary
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.