3D Stacked Memory Paired Channels for High-Capacity Access
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Solution Overview
Problem
Current computing systems, particularly those utilizing artificial neural networks, face challenges in efficiently accessing large data sets due to the limitations of two-dimensional integrated circuits (ICs). The growing number of processors and data sets necessitate larger, faster, and more efficient memory solutions.
Innovation Solution
The development of a stacked memory device using three-dimensional integrated circuits (3D-ICs) with multiple memory dies stacked over a base die. This configuration allows for flexible channel routing, enabling simultaneous or near-simultaneous read and write access to multiple memory dies without compromising speed or efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to support growing data sets, then memory bandwidth and access speed tend to decrease
Solution Approach 1:
The patent transitions from two-dimensional planar memory expansion to three-dimensional stacked memory architecture. Multiple memory dies are stacked vertically with interconnect layers enabling communication between dies, allowing memory capacity to scale in the vertical dimension while maintaining horizontal access speeds through parallel channel architecture.
Solution Approach 2:
The memory system is divided into multiple independent memory dies, each with its own command decoder and interface. These dies are organized into paired channels that can operate simultaneously, allowing the system to scale capacity by adding segments while maintaining access speed through parallel operation of segmented channels.
2Productivity
If multiple memory channels are accessed simultaneously to increase bandwidth, then power consumption increases
Solution Approach 1:
The patent combines multiple memory channels into paired channel groups that share common interconnect resources and command decoding logic. By merging channels into pairs that can be selectively activated, the system achieves high bandwidth when needed while reducing power consumption by keeping unused channels in a low-power state rather than running all channels continuously.
3Quantity of substance
If memory capacity is expanded without increasing power consumption, then access latency increases
Solution Approach 1:
Command decoders are distributed across multiple memory dies rather than centralized in one location. This preliminary distribution of decoding functionality allows each die to independently decode commands for its local memory cells, eliminating the time required for commands to travel across the entire memory array and reducing access latency while supporting expanded capacity.
Data Source
AI summary
A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.