Stacked Memory Peripheral Circuitry for Higher Density DRAM
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Solution Overview
Problem
Increasing memory storage density in semiconductor devices is challenging due to physical limitations, electrical interference, and manufacturing difficulties, particularly in managing peripheral circuitries that are traditionally integrated with memory arrays, limiting the separation distance and thermal budgets.
Innovation Solution
The peripheral circuitries are divided into two parts, with one part manufactured with memory arrays and the other separately, allowing vertical integration and independent thermal management, enabling reduced separation distances and larger via pitches, thus enhancing storage density and manufacturing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If peripheral circuitries are traditionally integrated with memory arrays, then device functionality is achieved, but separation distance is limited and manufacturing flexibility is reduced
Solution Approach 1:
The peripheral circuitries are divided into two separate parts: one part manufactured with the memory array on the first semiconductor structure, and another part manufactured separately on the second semiconductor structure. This segmentation allows independent optimization of each part's manufacturing process and enables greater manufacturing flexibility while reducing integration complexity through separate fabrication.
Solution Approach 2:
The patent transitions from traditional lateral integration to vertical integration by stacking the first semiconductor structure (with memory array and first peripheral circuitry) over the second semiconductor structure (with second peripheral circuitry). This dimensional change increases separation distance between circuitry parts while maintaining compact form factor, and enables independent thermal management of each layer.
2Productivity
If peripheral circuitries are separated into two parts with vertical integration, then manufacturing yield and flexibility improve, but device structure becomes more complex
Solution Approach 1:
By segmenting the peripheral circuitries into two separately manufactured parts, each part can be optimized for its specific manufacturing requirements. The first part is fabricated with the memory array using standard processes, while the second part can use specialized processes, improving overall manufacturing yield despite increased structural complexity.
Solution Approach 2:
The second semiconductor structure containing the second peripheral circuitry is placed within or under the first semiconductor structure. This nesting approach consolidates the multi-part device into a compact stacked architecture, reducing the overall space required and making the complex structure more manageable while maintaining high manufacturing yield.
3Quantity of substance
If separation distance between peripheral circuitries is reduced, then storage density increases, but electrical interference may increase
Solution Approach 1:
The patent reduces the lateral separation distance between peripheral circuitries by moving one part to a different vertical level on a stacked structure. This vertical separation in the third dimension maintains electrical isolation and reduces interference while allowing closer lateral packing, thereby increasing memory cell capacity without sacrificing signal integrity.
Solution Approach 2:
The patent introduces intermediate structures including bonding layers, dielectric materials, and conductive interconnection structures that mediate between the two separated peripheral circuitry parts. These intermediaries provide electrical isolation to prevent interference while enabling controlled signal transmission, allowing reduced separation distance and increased storage density.
4Manufacturing precision
If larger via pitches are used, then manufacturing consistency improves, but interconnection density decreases
Solution Approach 1:
By transitioning to vertical interconnections through stacked structures, the patent can use larger via pitches in the lateral direction while maintaining adequate interconnection density through the vertical dimension. The multi-layer stacking provides additional interconnection pathways, compensating for reduced lateral density and improving manufacturing consistency.
Data Source
AI summary
Systems, devices, methods for managing peripheral circuitries in semiconductor devices are provided. In one aspect, a semiconductor device includes a first semiconductor structure that includes a memory array and a first circuitry coupled to the memory array and a second semiconductor structure that includes a second circuitry. The first semiconductor structure includes a first bonding layer, and the second semiconductor structure includes a second bonding layer. The first bonding layer and the second bonding layer are in contact with each other. The first circuitry and the second circuitry are coupled together.