Stacked Memory Cell Layout With Peripheral CMOS Control Logic
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and reducing the size of memory devices while maintaining performance and simplifying designs, as processing conditions and complex control logic structures hinder these advancements.
Innovation Solution
The formation of microelectronic devices with vertically stacked memory cells and control logic regions, allowing for reduced horizontal footprint and increased memory density, utilizing complementary metal-oxide-semiconductor (CMOS) devices and circuitry for efficient control operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are integrated within the base control logic structure underlying the memory array, then memory device performance is improved, but the horizontal footprint and device complexity increase
Solution Approach 1:
The patent transitions from a two-dimensional planar integration of control logic devices to a three-dimensional vertical stacking architecture. Control logic devices are positioned in peripheral regions adjacent to the memory array rather than being embedded within the memory cell structure, allowing vertical extension without increasing the horizontal footprint of the active memory area. This dimensional reorganization enables enhanced performance through improved connectivity while maintaining compact form factor.
2Quantity of substance
If the density and complexity of the memory array are increased, then memory capacity is improved, but the control logic devices consume more real estate and reduce memory density
Solution Approach 1:
The patent segments the memory device into distinct functional regions: a central memory array region for high-density storage and peripheral control logic regions for control functions. This spatial segmentation allows the memory array to achieve high density through vertical stacking while control logic devices are accommodated in separate peripheral areas, preventing them from consuming valuable real estate within the memory array structure itself.
3Manufacturing precision
If processing conditions are optimized for memory array formation, then memory cell quality is improved, but the configurations and performance of control logic devices are limited
Solution Approach 1:
The patent employs selective processing sequences where control logic devices are formed in peripheral regions before the memory array is constructed in the central region. This preliminary formation of control logic structures allows them to be processed under optimized conditions for their specific requirements, while subsequent memory array formation can proceed with processing conditions optimized for high-density memory cell quality, without mutual interference.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically overlying the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region configured to effectuate control operations for memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region and a second control logic device region configured to effectuate control operations for memory cells of the second memory array region. Related memory devices, electronic systems, and methods are also described.