Stacked Memory Architecture with Distributed Peripheral Circuits
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Solution Overview
Problem
Existing memory devices face challenges in maximizing storage density and minimizing device size due to the large area occupied by peripheral circuits, which complicates routing and leads to wasted space.
Innovation Solution
The memory device employs a stacked semiconductor structure arrangement where the peripheral circuits are distributed at gaps of control circuits, with connection structures penetrating through the second semiconductor structure to connect with interconnect layers, allowing for efficient routing on the back side and reducing the area occupied by peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuits are distributed in a conventional planar layout, then routing is simplified, but the device area increases and storage density decreases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Peripheral circuits are distributed across multiple layers (first semiconductor layer, second semiconductor layer, and interconnect layers), allowing routing to occur in the vertical dimension through vias and through-silicon vias. This dimensional change reduces the lateral area required while providing additional routing paths that avoid conflicts.
Solution Approach 2:
The peripheral circuits are segmented and distributed across multiple discrete locations: some in the first semiconductor layer, others in the second semiconductor layer, and interconnected through the interconnect layers. This segmentation allows different circuit functions to be placed in optimal locations, reducing the area required for any single large peripheral circuit block while simplifying local routing.
2Quantity of substance
If peripheral circuits occupy large area, then routing is easier, but storage density is reduced
Solution Approach 1:
By utilizing the vertical dimension with multiple stacked layers, the patent achieves high storage density in the lateral plane while providing sufficient routing resources in the vertical dimension. Through-silicon vias and interconnect layers enable complex routing without requiring large lateral areas, thus maintaining both high storage density and routing capability.
Solution Approach 2:
The patent implements a nested hierarchical structure where memory cell arrays are stacked vertically with peripheral circuits distributed in intervening layers. The interconnect layers are nested between functional blocks, and vias are nested within the stack to provide vertical connectivity. This nesting allows efficient space utilization while maintaining routing pathways.
Data Source
AI summary
Examples of the present application provide a memory device. The memory device includes: a first semiconductor structure including a memory cell array; a second semiconductor structure including at least a plurality of first control circuits and at least part of a peripheral circuit distributed at gaps of the plurality of first control circuits, wherein the first semiconductor structure and the second semiconductor structure are stacked and connected; a first interconnect layer located on a side of the second semiconductor structure that is away from the first semiconductor structure; and a plurality of connection structures penetrating through part of the second semiconductor structure, wherein one end of each connection structure is connected with the at least part of the peripheral circuit at the gaps, and the other end is connected with the first interconnect layer.