Stacked Memory Data Timing Alignment via Replica Path Phase Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In stacked semiconductor memory devices, variations in process-voltage-temperature (PVT) across core dies introduce delays in data propagation through silicon vias (TSVs), leading to potential data overlap and alignment issues between core dies and the interface die.
Innovation Solution
The implementation of data aligner circuits with adjustable delay circuits in both the interface die and core dies, utilizing a replica path with a phase detector to align data timing. This includes a state machine that adjusts delays based on phase differences and enters fast alignment modes, such as CFAM, to correct for systemic errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is propagated through TSVs between interface die and core die, then data transmission is enabled, but delays and alignment issues occur due to PVT variations
Solution Approach 1:
The patent applies preliminary action by measuring and adjusting delays in a replica path before actual data transmission occurs. The delay adjustment is performed in advance using test patterns, and the adjusted delay values are stored for use during normal operation, thereby compensating for PVT variations before they affect data alignment.
Solution Approach 2:
The patent uses a replica path that copies the actual signal path through TSVs between interface die and core die. This replica path includes identical or substantially similar logic elements and TSVs, allowing delay measurement and adjustment to be performed on a copy of the system, which then informs the adjustment of the actual data path without interfering with normal operation.
2Reliability
If delay adjustment is performed continuously to maintain alignment, then data timing alignment is improved, but power consumption and operational complexity increase
Solution Approach 1:
The patent implements periodic action by performing delay measurements and adjustments at specific intervals rather than continuously. The system enters a test mode periodically to measure delays in the replica path, adjusts the delay values, and then returns to normal operation mode, thereby maintaining alignment while minimizing the time spent in high-power test mode.
Solution Approach 2:
The patent performs delay adjustment in advance during initialization or test modes, and then uses the pre-adjusted delay values during normal operation without requiring continuous adjustment. This preliminary adjustment reduces the need for ongoing power-consuming delay tuning operations.
3Productivity
If fast alignment mode is entered to correct systemic errors, then alignment speed is improved, but the frequency of mode switching may cause instability
Solution Approach 1:
The patent uses feedback by continuously monitoring the delay measurements from the replica path and comparing them against target values. The system enters fast alignment mode when the feedback indicates a significant deviation requiring rapid correction, and transitions back to normal operation when alignment is achieved, thereby using mode switching only when necessary and maintaining stability.
4Measurement precision
If replica path with phase detector is used to measure delays, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the replica path to serve multiple functions: it acts as both a delay measurement path and a functional copy of the signal path. The same logic elements and TSVs in the replica path are used for both measuring delays and representing the actual signal behavior, thereby reducing the need for separate dedicated measurement circuits.
Data Source
AI summary
Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.