Stacked Memory PHY Floorplan for Higher Bandwidth in Less Die Area
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Solution Overview
Problem
Existing memory interface layouts that arrange PHY blocks in a single column on each side of a die lead to increased die area and aspect ratio skew, especially when scaling for AI or high bandwidth applications, resulting in larger package sizes and potential loss of pin-to-pin compatibility.
Innovation Solution
A stacked PHY floorplan is implemented, arranging PHY blocks in two columns on each side of the die, allowing for reduced die height and maintaining aspect ratio while increasing the number of channels without significantly increasing area, and sharing clock resources between adjacent PHY blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If PHY blocks are arranged in a single column on each side of the die, then the layout is simple and easy to manufacture, but the die area increases and aspect ratio becomes skewed
Solution Approach 1:
The patent transitions from a single-column arrangement to a multi-column stacked arrangement, utilizing the second dimension (horizontal placement of multiple columns) to reduce the vertical height requirement. This dimensional change allows PHY blocks to be distributed across multiple columns, thereby reducing die height while maintaining manufacturing simplicity through standardized column-based layout patterns.
2Ease of manufacture
If PHY blocks are arranged in a single column on each side of the die, then the layout is simple, but the die height increases by up to 50%
Solution Approach 1:
The patent distributes PHY blocks across multiple columns arranged horizontally, converting a vertical stacking problem into a horizontal distribution solution. This dimensional change reduces die height by up to 50% while maintaining layout simplicity through systematic column-based organization of PHY blocks.
Solution Approach 2:
The patent segments the single column of PHY blocks into multiple columns, dividing the vertical arrangement into horizontal segments. This segmentation allows the same number of PHY blocks to be accommodated with reduced height by distributing them across multiple column segments arranged side-by-side.
3Productivity
If more channels are added for high bandwidth applications, then the data transfer capacity increases, but the die area and package size increase
Solution Approach 1:
The patent uses multi-column stacking to accommodate additional channels for high bandwidth applications without proportionally increasing die area. By arranging PHY blocks in multiple columns, the layout efficiently packs more channels into the available space, supporting increased bandwidth while controlling die area growth.
4Use of energy by moving object
If PHY blocks are arranged in adjacent columns, then clock resources can be shared between blocks, but the layout complexity increases
Solution Approach 1:
The patent merges clock resources between adjacent PHY blocks in the multi-column arrangement, allowing shared clock infrastructure to reduce power consumption. This merging approach enables resource optimization while the systematic column-based layout maintains manageable complexity through regular patterns.
Data Source
AI summary
A die includes a first set of physical layer (PHY) blocks arranged in a first column, wherein the first column extends along a side of the die. The die also includes a second set of PHY blocks arranged in a second column adjacent to the first column. The first set of PHY blocks include a first PHY block, the second set of PHY blocks include a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.