Stacked Ferroelectric Memory Pillars for Reliable 3D Integration

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Solution Overview

Problem

Current three-dimensional semiconductor storage devices face challenges in achieving high reliability due to integration limitations and operational stability, particularly in multilayer storage configurations where memory cells are stacked vertically.

Innovation Solution

A memory device is designed with a stacked body of conductor-including layers and insulating films, featuring pillar bodies with semiconductor and ferroelectric layers, where semiconductor members are separated by insulator pillars, and a method involving sacrificial film removal and ferroelectric layer formation to enhance reliability and integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multilayer storage devices are developed to achieve high integration, then integration density is improved, but operational reliability deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidoperational reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The device is divided into multiple stacked memory layers, each containing separated first and second semiconductor members that are electrically isolated. This segmentation allows independent operation of each layer, maintaining reliability while achieving high integration density through vertical stacking

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulator films are introduced as intermediary layers between conductor-including layers and between semiconductor members. These insulator films prevent electrical interference and leakage between adjacent layers and components, ensuring stable operation in the multilayer configuration

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If semiconductor members are placed in contact with conductive pillars in stacked layers, then integration is improved, but leakage current increases

Engineering Contradiction:
ImproveintegrationVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

Each semiconductor member is electrically separated from others through insulator films, creating isolated electrical pathways. This segmentation prevents leakage current between adjacent semiconductor members while maintaining integration through vertical stacking and controlled contacts with conductive pillars

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulator films serve as intermediary layers between semiconductor members and between semiconductor members and conductor-including layers. These intermediaries block unwanted electrical leakage while allowing controlled electrical contact where needed, reducing harmful leakage current

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If threshold voltage stability is improved through material selection, then operational stability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveoperational stabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent specifies particular material compositions and structural parameters (such as layer thicknesses and conductivity types) to achieve stable threshold voltage. By controlling these parameters during manufacturing, operational stability is improved while keeping the manufacturing process manageable through standardized material selections

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables highly reliable operations and manufacturing of memory devices with reduced leakage current and stable threshold voltage, improving integration density and operational stability.

Implementation Method 1

each conductor-including layer includes a semiconductor member in contact with the first and second conductive pillars, an electrode film and a ferroelectric layer between the semiconductor member and the electrode film

Methodology Applied
Scientific EffectFerroelectricity:

Data Source

PatentUS20230371266A1Memory device and method for manufacturing therefor
Publication Date: 2023.11.16 SUNRISE MEMORY CORP
  • US20230371266A1 patent drawing
  • US20230371266A1 patent drawing
  • US20230371266A1 patent drawing

AI summary

A memory device includes a stacked body of alternately arranged conductor-including layers and insulating films in the first direction and pillar bodies within the stacked body. Each pillar body includes first and second conductive pillars and an insulator pillar located between the first conductive pillar and the second conductive pillar. Each conductor-including layer includes a semiconductor member, an electrode film and a ferroelectric layer provided between the semiconductor member and the electrode film. The semiconductor members in the multiple conductor-including layers are separated from each other in the first direction.