Stacked Memory Pinout Design for Signal Integrity
Solution Overview
Problem
The increasing demand for higher data storage density in smaller consumer electronic devices poses challenges for traditional semiconductor memory packaging, particularly in minimizing signal integrity issues and optimizing pinout designs for stacked semiconductor memory devices.
Innovation Solution
A stacked semiconductor memory package design featuring an arrow-shaped configuration of NVM dies with half forming a staircase in one direction and the other half rotated 180° to continue the stack, along with a surface mount pinout design that minimizes high-speed signal distance, avoids signal crossings, and optimizes pin placement for improved signal integrity, using a package substrate with conductive vias and wire bonds for communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional semiconductor memory packaging is used, then manufacturing simplicity is maintained, but data storage density in smaller devices cannot be achieved
Solution Approach 1:
The patent transitions from traditional planar packaging to a three-dimensional stacked configuration where multiple NVM dies are arranged vertically in an arrow-shaped stack. This dimensional change allows significantly higher data storage density within a reduced footprint by utilizing the vertical dimension for stacking multiple memory layers.
Solution Approach 2:
The patent implements a nested structure where multiple NVM dies are stacked within a single package substrate, with each die containing memory cells nested within the previous layer. This nesting approach maximizes storage capacity within a compact volume by systematically organizing multiple memory layers in a hierarchical fashion.
2Reliability
If wire bonds are used for electrical connections, then ease of manufacture is maintained, but signal integrity deteriorates due to longer bond lengths
Solution Approach 1:
The patent optimizes wire bond parameters by minimizing bond length through strategic placement of bond pads and adjustment of wire bond angles. By changing the geometric parameters of the connection path and reducing the physical length of wire bonds, signal integrity is improved while maintaining the manufacturability of the wire bonding process.
3Reliability
If pinout design is not optimized, then manufacturing simplicity is maintained, but high-speed signal transmission performance deteriorates
Solution Approach 1:
The patent applies local quality optimization to the pinout design by differentiating signal routing for high-speed versus low-speed signals. High-speed differential pairs are assigned specific pin locations with controlled impedance characteristics and minimized crossing points, while other pins serve different functions. This localized optimization of pin assignments improves high-speed signal transmission without requiring complete redesign of the entire package.
Solution Approach 2:
The patent employs asymmetric pinout design where the arrangement of pins is optimized specifically for high-speed differential signal pairs rather than using a symmetric pattern. The pin locations are strategically positioned to minimize signal path length and avoid crossings, creating an asymmetric layout that prioritizes signal integrity over manufacturing simplicity.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit ("IC") package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.