3D Stacked Memory Device Pitch Reduction via Nested Insulation
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Solution Overview
Problem
Current memory devices face challenges in enhancing memory density due to limitations in the arrangement and spacing of semiconductor members and charge storage members, which affect the overall capacity and efficiency of memory storage.
Innovation Solution
The memory device incorporates a specific configuration with multiple conductive and semiconductor layers, charge storage members, and insulating layers arranged in a manner that allows for closer spacing and efficient use of space, including the use of non-conductive and conductive charge storage members, and resistance change members, to improve memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor members and charge storage members are arranged with larger spacing for ease of manufacture, then manufacturing precision is improved, but memory density deteriorates
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked configuration, arranging semiconductor members and charge storage members in multiple layers vertically. This dimensional change allows closer spacing in the horizontal plane while maintaining manufacturability through vertical separation, thereby increasing memory density without compromising manufacturing precision.
Solution Approach 2:
The patent implements a nested structure where charge storage members are positioned between and around semiconductor members in a stacked configuration. Multiple functional layers are nested within each other vertically, allowing compact arrangement with smaller pitch while maintaining adequate spacing for manufacturing. The insulating layers are nested between conductive layers, creating a compact yet manufacturable structure.
2Quantity of substance
If multiple conductive and insulating layers are added to increase memory density, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent designs the stacked structure where each layer serves multiple functions. The insulating layers provide both electrical isolation and structural support. The charge storage members serve as both storage elements and spacers for positioning semiconductor members. This multi-functionality reduces the need for additional dedicated layers, increasing memory density while controlling device complexity.
Solution Approach 2:
The patent combines multiple functional elements into integrated stacked units. Conductive layers and insulating layers are merged into alternating stacked sequences. Charge storage members and semiconductor members are combined in vertical stacks where they mutually support each other's positioning. This merging approach increases density while managing complexity through integrated design.
Data Source
AI summary
A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.