Stacked Memory POP Structure With Fan-Out SiP Interconnect
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Solution Overview
Problem
Traditional substrate manufacturing techniques are inadequate to support the increasing integration levels of front-end chip manufacturing, leading to higher costs and longer processing times, especially with the current line width/line spacing limitations and the need for multiple substrate layers.
Innovation Solution
A stacked memory package-on-package (POP) structure is achieved through a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit SiP package unit, connected via wire bonding and rewiring layers, eliminating the need for TSV holes and allowing for high-density, high-integration packaging with reduced line width/line spacing to 1.5 μm/1.5 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional substrate manufacturing techniques are used to support increasing integration levels, then the number of substrate layers increases, but the overall cost increases and processing time increases
Solution Approach 1:
The patent transitions from traditional two-dimensional substrate layer stacking to a three-dimensional package-on-package structure. Memory chips are stacked vertically and bonded to a substrate, with wire bonding structures extending upward to connect to peripheral circuits. This dimensional change allows higher integration without proportionally increasing substrate layer count, as connections are made in the vertical dimension through wire bonds rather than through additional substrate layers.
2Quantity of substance
If more chip I/O are placed on substrates, then the number of substrate layers increases, but the manufacturing process reaches its limits with minimum line width/line spacing of 20 μm/20 μm
Solution Approach 1:
The patent segments the circuit connections into two distinct parts: wire bonding structures that carry signals vertically from memory chips to the substrate, and peripheral circuits that are separately bonded to the substrate. This segmentation allows chip I/O to be increased without requiring higher manufacturing precision on the substrate itself, as the fine-pitch connections are made through wire bonding rather than through substrate trace routing.
3Adaptability or versatility
If advanced packaging techniques such as 2.5D & fan-out wafer level advanced packaging are used, then integration requirements are met, but the cost is higher and processing time is longer
Solution Approach 1:
The patent employs wire bonding structures that are self-aligned to the memory chips through the encapsulating layer. The wire bonding structures extend upward from the substrate and automatically align with bonding pads on the memory chip surfaces during the bonding process. This self-alignment mechanism eliminates the need for complex alignment procedures and reduces processing time compared to advanced packaging techniques that require precise pre-alignment of multiple layers.
Data Source
AI summary
A stacked memory POP structure and method are disclosed. The POP structure includes a first package unit of three-dimensional memory chip package and a system-in-package (SiP) package unit of two-dimensional fan-out peripheral circuit. The first package unit includes: memory chips laminated in a stepped configuration; wire bonding structures; and a first encapsulating layer. The SiP package unit includes: a first rewiring layer; a peripheral circuit chip a second rewiring layer bonded to the peripheral circuit chip; metal connection pillars electrically connected with the first rewiring layer and the second rewiring layer; a second encapsulating layer, which encapsulates the peripheral circuit chip and the metal connection pillars; and metal bumps on the first rewiring layer. The wire bonding structures are wire-bonded to the second rewiring layer to connect the memory chips to the second rewiring layer, thereby achieving attachment between the first package unit and the SiP package unit.