Semiconductor Device With Stacked Memory Power Gating
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Solution Overview
Problem
Existing semiconductor devices face challenges in uniformly managing power consumption for data transfer across memory cell arrays and limiting power consumption due to the increased area occupied by memory cell arrays, leading to inefficient arithmetic operations and high power usage.
Innovation Solution
A semiconductor device with stacked memory layers and a driver circuit layer, utilizing oxide semiconductors, where data transfer is controlled through write and read word/bit lines, allowing independent power gating of memory cell arrays not involved in arithmetic processing, and using a driver circuit to manage data transfer across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cell arrays are placed side by side to increase data capacity, then the area occupied by memory cell arrays increases, but power consumption becomes non-uniform across arrays leading to limited freedom in selecting storage locations
Solution Approach 1:
The memory device is divided into multiple independently controllable memory cell arrays (first memory cell array and second memory cell array), each with its own power supply control capability. This segmentation allows selective power gating of individual arrays, enabling uniform power consumption management across all arrays regardless of their position, thereby resolving the non-uniform power consumption issue while maintaining increased data capacity.
2Quantity of substance
If memory cell arrays are positioned apart from the arithmetic circuit to increase memory capacity, then data transfer power consumption increases
Solution Approach 1:
The patent implements dynamic power supply control where the power supply to each memory cell array can be independently adjusted based on operational needs. During arithmetic operations, only the actively used memory cell array maintains power supply, while others are powered down. This dynamic control eliminates unnecessary data transfer power consumption for inactive arrays while preserving the ability to store large amounts of data across multiple arrays positioned at different locations.
3Productivity
If all memory cell arrays remain active to provide data for arithmetic operations, then power consumption increases for arrays not directly contributing to computation
Solution Approach 1:
The patent applies partial action by activating only the specific memory cell array needed for current arithmetic operations, rather than keeping all arrays active. The power supply control circuit selectively enables power to the required memory cell array while disabling power to others, ensuring that power consumption is minimized while arithmetic operations proceed efficiently with the necessary data available.
Data Source
AI summary
A semiconductor device having a novel structure is provided. The semiconductor device includes memory layers and a driver circuit layer. The memory layers are stacked over the driver circuit layer and each include a memory cell array including a plurality of memory cells. Writing or reading of data to or from one of the memory cells is controlled with a write word line, a read word line, a write bit line, and a read bit line. The driver circuit layer includes a driver circuit portion configured to drive the write word line, the read word line, the write bit line, and the read bit line; and an arithmetic circuit portion. The driver circuit portion includes a plurality of driver circuits configured to control data writing or reading on the memory cell array basis. The arithmetic circuit portion is a circuit configured to perform arithmetic processing using the data retained in the memory cell array provided in each of the memory layers and read through the driver circuit portion.