Stacked Memory Channel Layout for Uniform Per-Die Power Delivery

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Solution Overview

Problem

Existing stacked semiconductor memory devices, such as 12H HBM devices, face challenges in achieving uniform power delivery across memory dies, leading to performance disparities and increased risk of failure due to uneven power distribution and thermal issues.

Innovation Solution

The implementation of a fine-grained channel configuration in HBM devices, where each channel can be individually configured to operate as either a 4N or 8N channel using electronic fuses, allows for uniform distribution of high-bandwidth channels across all memory dies, thereby improving power delivery efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power is delivered to stacked memory dies using conventional distribution methods, then all dies can be powered, but power delivery is uneven leading to performance disparities and thermal issues

Engineering Contradiction:
Improvepower delivery uniformityVSAvoidperformance consistency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the channel configuration into different bandwidth modes (4N and 8N channels) that can be independently assigned to different dies. This segmentation allows fine-grained control over power distribution, where higher bandwidth modes consume more power and can be selectively enabled on dies with better thermal management, thereby achieving more uniform power delivery across the stacked memory device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by allowing different dies to operate in different bandwidth modes based on their individual thermal and power characteristics. Each die can be configured with appropriate channel bandwidth (4N or 8N) according to its local conditions, creating non-uniform channel configurations that result in more uniform power and temperature distribution across the entire device.

Inventive Principle:
Principle #3Local quality

2Speed

If all channels are configured for high bandwidth (8N), then data throughput is maximized, but power consumption increases and thermal issues worsen

Engineering Contradiction:
Improvedata throughputVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent introduces dynamic configurability of channel bandwidth modes, allowing the system to adaptively switch between 4N and 8N channel configurations. This dynamic approach enables the memory device to optimize the balance between data throughput and power consumption by selecting appropriate bandwidth modes based on operational requirements and thermal conditions, rather than being fixed at maximum bandwidth.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the bandwidth parameter of channels from a fixed state to a configurable state, allowing transition between different bandwidth modes (4N and 8N). This parameter change capability enables flexible control over the trade-off between data throughput and power consumption, allowing the system to operate at optimal performance levels without excessive power draw.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If channel configurations are uniform across all dies, then manufacturing is simplified, but power distribution becomes uneven causing thermal hotspots

Engineering Contradiction:
Improveconfiguration uniformityVSAvoidthermal distribution
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent deliberately introduces asymmetry in channel configurations across different dies, where not all dies use the same bandwidth mode. This asymmetric configuration is designed to balance power distribution and eliminate thermal hotspots, trading off manufacturing simplicity for improved thermal management and device reliability.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20250194111A1Stacked memory device with improved per-die power delivery
Publication Date: 2025.06.12 MICRON TECHNOLOGY INC
  • US20250194111A1 patent drawing
  • US20250194111A1 patent drawing
  • US20250194111A1 patent drawing

AI summary

A memory device including a plurality of memory dies positioned in a stack, the plurality of memory dies including a first set of memory dies having a first number of channels configured according to a first configuration and a second number of channels configured according to a second configuration, wherein the first configuration comprises channels configured to have a first bandwidth and operate in a first bandwidth mode, and the second configuration comprises channels configured to have a second bandwidth and operate in a second bandwidth mode, and a second set of memory dies having a third number of channels configured according to the first configuration and a fourth number of channels configured according to the second configuration, wherein the first bandwidth is larger than the second bandwidth, the first number is larger than the third number, and the second number is larger than the fourth number.