Stacked Memory Chip Power Via Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor memory devices increase in integration density, there is a need to reduce the form factor while optimizing electrical characteristics across different regions, such as cell array and logic regions, to improve reliability.
Innovation Solution
The semiconductor memory device incorporates a stacked architecture with a cell chip and a core/peripheral chip, featuring interlayer insulating layers, power delivery network patterns, and penetration vias to connect transistors to the power delivery network, optimizing electrical connections and reducing interconnection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to improve productivity, then more circuits can be formed within limited chip area, but the form factor must be reduced and electrical characteristics must be optimized across different regions
Solution Approach 1:
The semiconductor device is divided into multiple substrates (first substrate with cell array region, second substrate with logic region) that are stacked and bonded together. This segmentation allows each substrate to be optimized independently for its specific function while achieving high integration density through vertical stacking, thereby maintaining electrical characteristics despite increased productivity requirements
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By forming circuits on multiple substrates stacked in the vertical direction and connecting them through penetration vias, the device achieves higher integration density without compromising electrical characteristics, as power delivery and signal routing are optimized in the vertical dimension
2Productivity
If more circuits are formed within limited chip area to improve productivity, then integration density increases, but interconnection density must be reduced to lower parasitic capacitance
Solution Approach 1:
The patent moves interconnections from a planar two-dimensional arrangement to a three-dimensional stacked configuration. Penetration vias provide vertical interconnection paths between substrates, reducing the need for extensive planar interconnection lines and thereby lowering parasitic capacitance while maintaining high integration density through vertical circuit stacking
Solution Approach 2:
Penetration vias act as intermediary elements that provide direct vertical electrical connections between the first substrate (cell array region) and the second substrate (logic region). This intermediary connection method reduces the need for long planar interconnection lines, thereby reducing parasitic capacitance while enabling high integration density through compact vertical stacking
3Productivity
If form factor is reduced to improve productivity, then chip area decreases, but electrical characteristics must be maintained across different regions
Solution Approach 1:
The patent reduces form factor by stacking substrates in the vertical direction rather than expanding in the planar direction. This three-dimensional arrangement compactly integrates the cell array region and logic region within a small footprint while maintaining electrical characteristics through optimized vertical power delivery networks and penetration via connections
Solution Approach 2:
Each substrate is optimized with local quality tailored to its specific function: the first substrate contains the cell array region with appropriate interlayer insulating layers, while the second substrate contains the logic region with transistors and power delivery network patterns. This localized optimization maintains electrical characteristics for each region's specific requirements while achieving compact form factor through vertical stacking
Data Source
AI summary
An example semiconductor memory device includes a first substrate, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, a second interlayer insulating layer covering an active surface of the second substrate, a third interlayer insulating layer covering an inactive surface of the second substrate, a power delivery network pattern disposed in the third interlayer insulating layer, an inner penetration via, a first outer penetration via, and a second outer penetration via. The inner penetration via extends through the second substrate and connects transistors with the power delivery network pattern. The first outer penetration via extends through at least one of the second interlayer insulating layer, the second substrate, and the third interlayer insulating layer. The second outer penetration via extends through the second interlayer insulating layer, the second substrate, and the third interlayer insulating layer.