Stacked Memory and Recess Channel Circuit Layout for Smaller Footprint
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in increasing data storage capacity while maintaining a compact form factor, as the area occupied by peripheral circuits increases with the number of word lines and transistors, hindering high integration and planar size reduction.
Innovation Solution
A semiconductor device structure is implemented with a vertical stacking of memory cell arrays and peripheral circuits, incorporating planar channel transistors and recess channel transistors, which allows for efficient use of space and reduces the area occupied by peripheral circuits, enabling higher integration and smaller form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines and transistors is increased to improve data storage capacity, then the degree of integration is improved, but the area occupied by peripheral circuits increases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional vertical stacking, where the cell area is stacked above the peripheral circuit area in the vertical direction. This dimensional change allows the peripheral circuit area to remain compact while accommodating increased data storage capacity through additional vertical layers of word lines and memory cells.
Solution Approach 2:
The patent divides the semiconductor device into distinct functional areas: a cell area containing memory cell arrays and a peripheral circuit area containing control circuits. These segmented areas are arranged in different vertical layers, allowing independent optimization of each area while maintaining overall integration.
2Device complexity
If the number of stacks of word lines is increased to improve integration, then the degree of integration is improved, but the planar size increases
Solution Approach 1:
Multiple stacks of word lines are arranged in the vertical direction rather than spreading them out in the planar direction. The cell area is stacked above the peripheral circuit area, creating a three-dimensional structure that achieves high integration without increasing planar footprint.
Solution Approach 2:
The patent implements a nested structure where the cell area (containing memory cells and word lines) is stacked above the peripheral circuit area. This nesting arrangement allows multiple functional layers to occupy overlapping planar spaces at different vertical levels, maximizing integration density.
Data Source
AI summary
A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.