Stacked Memory Retiming Circuit for Synchronized Redundant Data
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Solution Overview
Problem
In stacked memory architectures, maintaining synchronization of read data with the overall memory system timing is challenging due to the lack of a separate timing signal for data transmitted from a redundant memory chip, leading to potential bad data sampling when using source-synchronous architectures.
Innovation Solution
The implementation of internal secondary signaling paths within the stacked memory chip stack allows for internal data transmission between chips, ensuring that read data from different chips are aggregated in the same timing domain before being transmitted to the controller, thereby preserving synchronization, and utilizing a redundant memory chip to replace faulty storage locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redundant memory chip is used to replace failed storage locations in stacked memory, then reliability is improved, but synchronization of read data with timing signals deteriorates due to lack of separate timing signal paths
Solution Approach 1:
The patent introduces an intermediary retiming circuit as a mediator between the redundant memory chip and the primary memory chip. This retiming circuit receives data from the redundant chip, retimes it to match the timing domain of the primary chip, and then forwards it. This intermediary component resolves the synchronization issue caused by the redundant chip lacking a dedicated timing signal path, while preserving the reliability benefits of redundancy.
2Device complexity
If data is transmitted from the redundant memory chip without a separate timing signal, then device complexity is reduced, but data sampling accuracy deteriorates leading to potential bad data
Solution Approach 1:
The retiming circuit performs self-service by automatically adjusting the timing of data received from the redundant memory chip. Instead of requiring an external separate timing signal path, the circuit autonomously retimes the data to match the primary chip's timing domain, ensuring accurate sampling without increasing overall system complexity.
Data Source
AI summary
A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.