Stacked Memory Refresh Control for Lower Slice Current Peaks
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Solution Overview
Problem
In stacked memory devices, the refresh operation for memory cells leads to increased current consumption when all slice chips are refreshed simultaneously, which can be inefficient and wasteful.
Innovation Solution
A control circuit is implemented to manage the refresh operations of each slice chip individually, alternating between different refresh modes (auto-refresh, smart-refresh, and skip-refresh) based on a refresh bank signal and clock signal, ensuring optimized power usage by varying the refresh operations across the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all slice chips are refreshed simultaneously, then data integrity is maintained across all memory cells, but current consumption increases significantly
Solution Approach 1:
The refresh operation is segmented by slice chip, with each slice chip (first slice chip and second slice chip) receiving independent refresh control signals from the base chip. This allows different slice chips to be refreshed at different times or in different modes, preventing simultaneous refresh of all chips and reducing peak current consumption while maintaining data integrity in each segment.
Solution Approach 2:
The refresh operation uses periodic clock signals to control the timing of refresh operations across different slice chips. By staggering the refresh timing using periodic actions with different phases or intervals for different slice chips, the system maintains refresh effectiveness while avoiding the current surge that would occur with simultaneous refresh.
2Reliability
If refresh operations are performed on all slice chips, then all memory cells are maintained, but power efficiency decreases
Solution Approach 1:
Different refresh modes are applied to different slice chips based on their specific requirements. The base chip can assign auto-refresh mode to some slice chips and skip-refresh mode to others, allowing each slice chip to receive the appropriate level of refresh attention. This local differentiation ensures that memory cells are maintained where needed while avoiding unnecessary refresh operations that would waste power.
Solution Approach 2:
The system performs partial refresh operations by selectively refreshing only certain slice chips or certain banks within slice chips based on actual needs. Instead of refreshing all slice chips uniformly, the base chip can identify which slice chips require refresh and apply refresh operations only to those, reducing overall power consumption while maintaining reliability where necessary.
Data Source
AI summary
A stack memory device includes a base chip, a first slice chip stacked over the base chip, and a second slice chip stacked over the first slice chip. The base chip includes a slice control circuit configured to control the first slice chip and the second slice chip such that a refresh operation is performed according to a refresh mode of the first slice chip and a refresh mode of the second slice chip when a refresh bank signal is generated that refreshes banks included in the first slice chip and the second slice chip.