Stacked Memory Die Repair Using Cross-Die Redundancy Paths
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Solution Overview
Problem
Existing memory systems face limitations in contact density, data rate, and storage density due to interconnection techniques in memory dies, which affect manufacturing yield and storage capacity.
Innovation Solution
Distribute memory access circuitry among multiple semiconductor dies in a stack, incorporating redundancy portions for efficient repair of failures, such as column failures and interconnection issues, by utilizing a second die to reroute signals through alternative paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional interconnection techniques are used in memory dies, then manufacturing process is simpler, but contact density and data rate are limited
Solution Approach 1:
The patent divides the memory system into multiple semiconductor dies stacked vertically, with each die containing memory arrays and access circuitry. This segmentation allows each die to have fewer, more manageable contacts while achieving higher overall contact density through the stacked architecture. The system distributes storage capacity and access pathways across multiple dies, resolving the contradiction between contact density and structural complexity.
Solution Approach 2:
The patent transitions from a planar, two-dimensional interconnection structure to a three-dimensional stacked architecture. By adding the vertical dimension, the system achieves higher contact density and data rate without proportionally increasing the complexity of individual die interconnections. The vertical stacking provides additional routing pathways and contact opportunities that would be impossible in a traditional planar design.
2Reliability
If redundancy portions are added for repair functionality, then reliability and manufacturing yield improve, but device complexity increases
Solution Approach 1:
The redundancy portions in each memory die are designed to serve multiple purposes: they can repair column failures, handle interconnection issues, and provide alternative data pathways. This multi-functionality allows the same structural element to address various failure modes, improving reliability without proportionally increasing complexity. The redundancy arrays are integrated into the normal memory operation, allowing them to function as part of the primary storage capacity when no failures occur.
3Quantity of substance
If multiple semiconductor dies are stacked, then storage capacity and data rate improve, but manufacturing complexity increases
Solution Approach 1:
By segmenting the total storage capacity across multiple identical or near-identical semiconductor dies, the patent simplifies the manufacturing process for each individual die while achieving high overall storage capacity. Each die can be manufactured using standardized processes, and the complexity of assembling multiple dies is managed through modular design and standardized interconnection interfaces. This segmentation approach allows for better yield management and easier repair than manufacturing a single large-capacity die.
Data Source
AI summary
Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.