Stacked Memory Device with Ring Isolation for Electrical Connection
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Solution Overview
Problem
Existing memory devices face challenges in achieving high memory capacity while maintaining efficient integration and electrical connectivity between components in a three-dimensional structure.
Innovation Solution
A memory device is constructed with a first substrate and a second substrate stacked on top, featuring a ring-shaped isolation structure that surrounds a conductor penetrating the second substrate, allowing for electrical coupling of transistors and external connection terminals, and utilizing a method of manufacturing that involves separate processes for each substrate layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions with stacked substrates, then memory capacity is improved, but electrical connectivity and integration efficiency deteriorate
Solution Approach 1:
The patent introduces a conductor that penetrates the second substrate to serve as an intermediary element, electrically coupling the first transistor on the first substrate to the external connection terminal above the second substrate. This mediator resolves the electrical connectivity issue in the three-dimensional stacked structure by providing a direct conduction path through the substrate layers.
Solution Approach 2:
The patent transitions from planar two-dimensional arrangement to three-dimensional stacked configuration by placing the second substrate above the first substrate, with the conductor extending vertically through the second substrate. This dimensional change increases memory capacity while the conductor maintains electrical connectivity across the stacked layers.
2Ease of manufacture
If separate processes are used for each substrate layer, then manufacturing flexibility is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory device into separate substrate layers (first substrate and second substrate) that can be manufactured independently through separate processes. Each substrate can be optimized and fabricated separately, then integrated together, providing manufacturing flexibility while managing complexity through modular segmentation.
Solution Approach 2:
The patent combines separately manufactured substrate layers into an integrated three-dimensional structure. The first substrate containing the first transistor is merged with the second substrate containing the external connection terminal, with the conductor providing electrical coupling between them, achieving both manufacturing flexibility and functional integration.
3Reliability
If a conductor penetrates the second substrate to connect transistors, then electrical connectivity is improved, but capacitance increases
Solution Approach 1:
The patent extracts the conductor from being part of the substrate material and makes it a distinct penetrating element that passes through the second substrate. This separation allows the conductor to provide necessary electrical connectivity while minimizing its interaction with the substrate, thereby reducing parasitic capacitance generated by the connection structure.
Data Source
AI summary
A first transistor is on the first substrate. A second substrate is above the first transistor. An external connection terminal is above the second substrate. A second transistor is on the second substrate. A first conductor penetrates the second substrate and electrically couples the first transistor to the external connection terminal. A first isolation structure, as viewed from a first direction, is ring-shaped and surrounds the first conductor, penetrates the second substrate, and isolates the second substrate. A memory cell array is electrically coupled to the first transistor and the second transistor.