Stacked Memory Device Routing Wires Non-Bonding Areas
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Solution Overview
Problem
Current memory devices face challenges in increasing their degree of integration, which is essential for reducing chip size and improving storage capacity, as they require separate spaces for signal and power lines, limiting their compactness.
Innovation Solution
The memory device incorporates a chip-to-chip structure where semiconductor chips with bonding and non-bonding areas are stacked, with routing wires formed in the uppermost metal layer of non-bonding areas, allowing for electrical connection without additional space, thereby reducing chip size and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If routing wires are placed in bonding areas to connect memory cell array and peripheral circuit, then electrical connection is achieved, but chip area is wasted and integration density is reduced
Solution Approach 1:
The chip surface is divided into bonding areas and non-bonding areas. Routing wires are selectively placed only in non-bonding areas, separating the functions of bonding and routing to optimize space utilization and reduce chip size.
Solution Approach 2:
The patent utilizes the vertical stacking of metal layers to provide additional routing dimensions. By distributing routing wires across multiple metal layers in non-bonding areas, the design achieves efficient signal routing without increasing chip footprint.
2Reliability
If separate spaces are allocated for signal lines and power lines, then electrical connection reliability is improved, but chip area increases
Solution Approach 1:
Signal lines and power lines are routed together in non-bonding areas using the same metal layers. This merging of routing paths for different electrical functions reduces the total area required while maintaining connection reliability through proper layer design.
Solution Approach 2:
The non-bonding areas serve multiple functions: they provide routing paths for both signal lines and power lines, and they enable electrical connection between stacked chips. This multi-functional use of space eliminates the need for separate dedicated areas for each function.
Data Source
AI summary
A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.