Stacked Memory Row Hammer Mitigation Through Die-Level Signaling
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Solution Overview
Problem
Row hammer attacks in stacked memory architectures can adversely affect neighboring memory cells, leading to data corruption and compromised security.
Innovation Solution
Distribute row hammer mitigation operations across multiple semiconductor dies by using counters to track access operations and exchange signaling between interface blocks to implement refresh commands for affected memory rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row hammer mitigation operations are concentrated on a single die, then the mitigation logic is simpler to implement, but the security and reliability against row hammer attacks is reduced
Solution Approach 1:
The patent divides the row hammer mitigation functionality across multiple semiconductor dies. Each die contains its own mitigation logic and counters, allowing independent detection and response to row hammer attacks. This segmentation enhances reliability by distributing the security function, preventing a single point of failure, and enabling parallel mitigation operations across different memory banks.
2Reliability
If access operations are frequently monitored with counters, then row hammer attacks are detected earlier, but the overhead and complexity of tracking and signaling increase
Solution Approach 1:
The patent implements counters and monitoring logic locally at each semiconductor die rather than centrally. Each die maintains its own access counters for local memory rows and can independently detect excessive access patterns. This local quality approach reduces the complexity of inter-die signaling while maintaining effective detection capability, as each die only needs to monitor its own local access patterns.
Solution Approach 2:
Each semiconductor die performs self-monitoring of its own access operations using local counters. The mitigation logic resides on the same die that experiences the attacks, allowing it to autonomously detect and respond to row hammer conditions without requiring constant external intervention. This self-service capability reduces overall system complexity while maintaining high detection effectiveness.
3Reliability
If refresh commands are issued for affected memory rows, then data integrity is maintained, but the performance and throughput of memory operations decrease
Solution Approach 1:
The patent implements counters that track access patterns before row hammer attacks can cause data corruption. By detecting excessive access attempts in advance and issuing refresh commands proactively, the system prevents data integrity failures rather than reacting after damage occurs. This preliminary action allows refresh operations to be scheduled at optimal times, minimizing their impact on overall memory throughput.
Solution Approach 2:
The patent uses periodic counter checking and conditional refresh operations based on monitored access patterns. Instead of continuous monitoring or forced periodic refreshes of all rows, the system periodically checks counters and issues refresh commands only when attack patterns are detected. This selective periodic action maintains data integrity for affected rows while preserving normal memory performance for unaffected operations.
Data Source
AI summary
Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.