Stacked Memory Section Yielding for Fault-Tolerant Die Stacks
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Solution Overview
Problem
The yield of semiconductor systems with stacked memory architectures is adversely affected due to compounded non-perfect yields in wafer stacks, leading to reduced performance and increased manufacturing costs and electronic waste.
Innovation Solution
Implement section yielding techniques by dividing semiconductor wafers into die units with multiple sections, evaluating their functionality, and disabling faulty sections to maintain the operation of the remaining stacks, thereby improving yield and reducing waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If section yielding is implemented by dividing wafers into die units with multiple sections, then manufacturing precision and yield are improved, but device complexity increases
Solution Approach 1:
The patent divides semiconductor wafers into multiple die units, and each die unit is further divided into multiple sections. This hierarchical segmentation allows independent evaluation and disabling of faulty sections without affecting the entire die unit or wafer, thereby improving yield while managing complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimension of organization by stacking multiple die units vertically to form three-dimensional stacked memory architectures. This vertical stacking transforms the traditional two-dimensional wafer layout into a three-dimensional structure, enabling higher density while maintaining the section-level fault isolation capability.
2Loss of substance
If faulty sections are disabled rather than discarding entire components, then loss of substance is reduced, but measurement precision requirements increase
Solution Approach 1:
The patent performs functionality evaluation of each section during the manufacturing process, before the die units are stacked and assembled into final memory devices. This preliminary testing allows faulty sections to be identified and disabled early, preventing waste of entire components while reducing the complexity of later testing and rework.
Data Source
AI summary
Methods, systems, and devices for section yielding in stacked memory architectures are described. A system that implements a stacked semiconductor architecture may include wafers that are divided into die units having multiple sections, and the sections may be coupled as die unit section stacks through a stack of wafers. After stacking the semiconductor wafers (e.g., before or after singulation of die stacks from the stacked wafers), functionality of the die unit section stacks may be evaluated. If a die unit section stack is found to include an error or relatively low performance, the die unit section stack may be disabled, such that other die unit section stacks of a stacked die assembly may be operated (e.g., operated in accordance with a capacity or throughput associated with the remaining memory die unit section stacks).