Stacked Memory Device With Segmented Control Circuit Layer
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Solution Overview
Problem
Next-generation memory devices require high integration and rapid speed with low power consumption, while existing resistive memory devices face challenges in efficiently managing stacked memory cells for high capacity and efficient operation.
Innovation Solution
A memory device architecture featuring a bank layer with stacked decks of memory cells and a control circuit layer with alternately arranged word line and bit line decoders, allowing for efficient selection and operation of memory cells through hierarchical structures and resistor patterns at intersecting points of word and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory cells are used to increase capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent mats (e.g., first mat, second mat) with each mat containing stacked decks of memory cells. Each mat can be independently controlled by dedicated control circuit regions, allowing the system to manage complexity through modular segmentation while achieving high capacity through the combination of multiple mats.
Solution Approach 2:
The patent transitions from a planar memory structure to a three-dimensional stacked structure where multiple decks of memory cells are vertically stacked. This dimensional change allows significantly more storage capacity within the same footprint while using hierarchical control circuits to manage the added complexity of vertical stacking.
2Quantity of substance
If multiple stacked decks are implemented, then capacity increases, but control circuit complexity increases
Solution Approach 1:
The control circuit layer is segmented into multiple control circuit regions (first control circuit region, second control circuit region, etc.) corresponding to different mats. Each control circuit region manages only its associated mat, reducing the complexity burden on any single control circuit while collectively providing comprehensive control for all stacked decks.
Solution Approach 2:
The control circuit regions are designed to be reusable and interchangeable across different mats. The same control circuit region design can be replicated for different mats, allowing a single control circuit implementation to manage multiple stacked decks through modular universality, thereby reducing overall control circuit complexity.
3Productivity
If hierarchical structure with word line and bit line decoders is used, then selection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The decoder system is segmented into separate word line decoder regions and bit line decoder regions positioned in different control circuit regions. This segmentation allows independent design and fabrication of decoder components, simplifying the manufacturing process while maintaining the hierarchical selection efficiency through modular assembly.
Solution Approach 2:
Different regions of the control circuit layer are assigned specific functions (word line decoding in some regions, bit line decoding in others) based on local requirements. This localized functional assignment optimizes selection efficiency for each region while allowing standardized manufacturing processes to be applied uniformly across the device.
Data Source
AI summary
A memory device may include a bank layer and a control circuit layer. The bank layer may be arranged on a semiconductor substrate. The bank layer may include a plurality of mats. Each of the mats may include a plurality of stacked decks. Each of the decks may include a plurality of memory cells. The control circuit layer may be arranged between the semiconductor substrate and the bank layer. The control circuit layer may include a plurality of control circuit regions corresponding to the mats, respectively. The stacked decks may include a plurality of stacked word lines and a plurality of stacked bit lines intersected with the stacked word lines. A word line decoder, for controlling the word lines, and a bit line decoder, for controlling the bit lines, may be alternately and repeatedly arranged in the control circuit layer.