Stacked Semiconductor Memory Device with Segmented Electrodes
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Solution Overview
Problem
Current stacked type semiconductor memory devices face challenges in achieving higher integration levels due to limitations in the design and manufacturing processes, particularly in forming memory cells and electrode structures that allow for increased density without compromising reliability and manufacturing complexity.
Innovation Solution
The semiconductor memory device design involves a stacked body with alternating insulating and electrode films, where semiconductor pillars and insulating members are arranged in a specific pattern to form memory cells, and a method that includes forming memory trenches, recesses, and charge storage members to enhance integration by reducing the volume of memory trenches and stress on the substrate, while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are integrated three-dimensionally in a stacked type structure, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The stacked body is divided into multiple memory regions with alternating insulating films and electrode films forming distinct layers. Semiconductor pillars are segmented and positioned at specific intersections, creating modular memory cell units that can be manufactured systematically through repeated patterning and deposition cycles.
Solution Approach 2:
The patent transitions from planar memory cell arrangement to three-dimensional stacked architecture. Memory cells are formed at intersections of electrode films extending in different directions (first direction and second direction) with semiconductor pillars extending in a third direction, utilizing vertical stacking to achieve higher integration density.
2Quantity of substance
If the volume of memory trenches is reduced to increase integration, then integration density is improved, but stress on substrate increases
Solution Approach 1:
The substrate stress is managed by segmenting the structure into alternating insulating films and electrode films in the stacked body. This layered configuration distributes mechanical stress across multiple interfaces rather than concentrating it on the substrate, enabling tighter integration without compromising substrate integrity.
3Reliability
If independent upper select gate lines are formed to improve reliability, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The select gate functionality is segmented into independent upper select gate lines that are separately formed and controlled. These independent gate lines are positioned at different levels within the stacked body, allowing selective activation of different memory regions and improving device reliability through redundant control paths.
Solution Approach 2:
The electrode films serve multiple functions: they act as word lines for memory cell selection, as upper select gate lines for region isolation, and as interconnect structures. This multi-functionality reduces the need for separate dedicated structures, managing manufacturing complexity while improving functionality.
Data Source
AI summary
A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.