Stacked Memory Segments for Word Line Assertion
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Solution Overview
Problem
Conventional semiconductor memory devices with longer Word Lines (WLs) suffer from degraded speed and inefficient layout due to aspect ratio issues, leading to wasted area and layout difficulties as memory devices increase in size.
Innovation Solution
The memory device is split into two segments with one positioned over the other, utilizing a 'flying Bit Line' scheme where BLs from the top segment go over the bottom segment in an upper metal layer, allowing two Word Lines to be activated in one cycle, thereby reducing WL lengths and improving efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device size increases, then storage capacity improves, but layout difficulty and aspect ratio issues worsen
Solution Approach 1:
The memory device is divided into two segments stacked vertically, with each segment containing memory cells and associated bit lines. This segmentation allows the memory array to be organized in a three-dimensional configuration, increasing storage capacity while maintaining manageable layout dimensions for each segment.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By positioning one segment over the other in the vertical dimension and routing bit lines through upper metal layers, the design achieves higher capacity without proportionally increasing the footprint area, thereby improving aspect ratio and layout efficiency.
2Area of stationary object
If Word Line length increases, then memory coverage area improves, but access speed degrades
Solution Approach 1:
The memory array is segmented into two stacked segments, each with its own shorter Word Lines. This segmentation reduces the length of individual Word Lines compared to a single large planar array, thereby improving access speed while maintaining comprehensive memory coverage through the vertical stacking arrangement.
Solution Approach 2:
By organizing memory cells across two vertical segments rather than expanding a single planar array, the patent reduces Word Line lengths in the horizontal plane. The vertical stacking allows the memory to cover the required area without proportionally increasing Word Line length, thus preserving access speed.
3Area of stationary object
If Word Line length increases, then memory coverage area improves, but layout efficiency worsens
Solution Approach 1:
The patent employs a three-dimensional stacked architecture where two memory segments are positioned vertically. This approach allows the memory device to achieve the required coverage area by utilizing the vertical dimension, thereby maintaining a favorable aspect ratio in the planar footprint and avoiding the layout inefficiencies associated with long Word Lines in a stretched planar configuration.
4Ease of operation
If single Word Line activation is used, then control simplicity is maintained, but productivity decreases
Solution Approach 1:
The control circuit is designed to simultaneously activate Word Lines in both segments as a coordinated preliminary action. This allows the memory system to prepare and execute dual-segment access in parallel, improving productivity by utilizing both segments during a single memory cycle while maintaining control simplicity through unified Word Line signaling.
Solution Approach 2:
By enabling simultaneous Word Line activation in both segments, the patent ensures continuous utilization of the memory resource. Both segments remain active and productive during each access cycle, eliminating idle time and maximizing throughput without complicating the control mechanism.
Data Source
AI summary
A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.