Stacked Memory Array Architecture With Shared Metallization
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Solution Overview
Problem
As microelectronic device designers aim to increase integration density and performance, the complexity and real estate consumption of control logic devices within memory devices hinder reductions in size and improvements in performance, particularly in memory arrays with increasing density and complexity.
Innovation Solution
A microelectronic device structure comprising a first and second memory array region with shared back-end-of-line structure and metallization levels, where the second device is attached to the first via oxide-to-oxide bonding, reducing the number of metallization and routing layers and facilitating increased memory cell density with improved data transmission speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control logic devices are increased in quantity and complexity to support larger memory arrays, then memory device functionality and control capability are improved, but device size and real estate consumption increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture by bonding multiple memory array regions vertically. This allows control logic devices to serve multiple memory regions through vertical stacking, increasing control capability without proportionally increasing the horizontal footprint of the device.
Solution Approach 2:
The shared back-end-of-line structure and metallization levels are designed to serve multiple memory array regions simultaneously. The control logic devices can control memory cells across different stacked regions, making the control infrastructure multi-functional and reducing the need for separate control logic for each memory region.
2Quantity of substance
If the number of metallization and routing layers is increased to support higher memory cell density, then memory cell density is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent merges the back-end-of-line structures and metallization levels of multiple memory array regions into a shared infrastructure. By combining these elements across stacked regions, the patent achieves higher memory cell density without proportionally increasing the complexity of metallization layers, as the same metallization structures serve multiple memory regions.
3Area of stationary object
If control logic devices are reduced in size to decrease overall device footprint, then device integration density is improved, but control performance and reliability may deteriorate
Solution Approach 1:
The patent utilizes vertical stacking to maintain adequate control logic device sizes for reliable operation while reducing the horizontal footprint. By arranging memory array regions in three dimensions, the control logic devices can remain sufficiently large for reliable control performance while the overall device occupies less planar area through vertical integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a higher density of memory cells within a given area while reducing the number of metallization levels, thereby enhancing performance and reducing fabrication costs, addressing the limitations of traditional microelectronic devices.
Implementation Method 1
the second device is attached to the first via oxide-to-oxide bonding
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region comprising memory cells, each of the memory cells comprising an access device and a charge storage device operably coupled to the access device. The first microelectronic device structure further comprises a first base structure comprising first control logic devices configured to effectuate one or more control operations of the memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region comprising additional memory cells, each of the additional memory cells comprising an additional access device and an additional charge storage device operably coupled to the additional access device. The second microelectronic device further a second base structure comprising second control logic devices configured to effectuate one or more control operations of the additional memory cells of the second memory array region. Related microelectronic devices, electronic systems, and methods are also described.