Stacked Memory I/O Circuit With Shared Receiver for Through-Electrode Layout
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Solution Overview
Problem
Stack type semiconductor memory devices require efficient signal transmission and reception mechanisms, but existing technologies face challenges in optimizing the layout and circuit area related to through electrodes and signal lines, leading to inefficiencies in multi-chip operations.
Innovation Solution
The semiconductor memory device design includes a core block, peripheral circuit block, and data input/output circuit that share a single receiver and transmitter for signal exchange through through electrodes, utilizing multiplexers and logic gates to manage multi-chip operation signals and control signal transmission, thereby reducing circuit area and preventing data collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple signal lines and transmission/reception circuits are used for through electrodes, then signal transmission capability is improved, but circuit area increases
Solution Approach 1:
The patent combines multiple signal lines into a single shared signal line that is time-multiplexed. The data input/output circuit shares one receiver and one transmitter among multiple signal lines, allowing sequential signal transmission instead of requiring simultaneous dedicated circuits for each line, thereby reducing circuit area while maintaining signal transmission capability.
Solution Approach 2:
The patent introduces dynamic time-multiplexing control where the data input/output circuit dynamically switches between different signal lines based on operation timing. The receiver and transmitter are dynamically allocated to different signal lines at different times, enabling flexible resource utilization and reducing the need for static dedicated circuits.
2Reliability
If multiple receivers and transmitters are allocated to different signal lines, then signal transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent makes a single receiver and transmitter universal by enabling them to handle multiple signal lines through time-multiplexing. The same receiver circuit serves multiple signal lines at different time intervals, and the same transmitter circuit similarly serves multiple lines, reducing the total number of circuits while maintaining reliable signal transmission across all lines.
Solution Approach 2:
The patent ensures continuous signal transmission capability across all signal lines by implementing time-multiplexed operation. Although a single receiver serves multiple lines, the systematic allocation of time slots ensures that each signal line receives continuous attention, maintaining reliable communication without requiring multiple simultaneous receivers.
3Productivity
If dedicated signal lines are used for each function, then signal transmission efficiency is improved, but layout flexibility decreases
Solution Approach 1:
The patent segments the time domain into different slots for different signal lines, allowing a single physical signal line to carry multiple logical signals sequentially. This temporal segmentation enables the same physical resource to serve multiple functions, improving layout flexibility while maintaining efficient signal transmission through structured time-multiplexed access.
Data Source
AI summary
A semiconductor memory device includes a core block including a plurality of unit memory blocks, a peripheral circuit block including a data input/output pad, a through electrode configured to exchange signals with another semiconductor memory device, and a data input/output circuit coupled to the through electrode, the core block, and the peripheral circuit block and configured to share one receiver in order to transmit a signal from the through electrode to the peripheral circuit block and in order to transmit a signal from the through electrode to the core block.