Stacked Semiconductor Memory with Shared Selecting Element
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges in simplifying the fabrication process, increasing integration degree, and reducing production costs, particularly in cross-point structures where variable resistance elements and selecting elements are difficult to pattern due to their large thickness and the need for intermediate electrodes.
Innovation Solution
The proposed electronic device features a semiconductor memory with a stacked structure comprising word lines, bit lines, and variable resistance layers, where a selecting element is shared between two memory cells, simplifying the fabrication process by eliminating the need for intermediate electrodes and allowing separate patterning of variable resistance and selecting elements, and maintaining proper operating characteristics with appropriate voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If variable resistance elements and selecting elements are patterned separately in cross-point structures, then manufacturing precision is improved, but device complexity increases due to the need for intermediate electrodes
Solution Approach 1:
The patent extracts the intermediate electrode from the structure by allowing bit lines to directly contact variable resistance elements. This eliminates the need for separate intermediate electrodes, reducing device complexity while maintaining the ability to pattern variable resistance elements and selecting elements separately with high precision.
Solution Approach 2:
The bit line serves multiple functions: it acts as both a selecting element (controlling current flow to specific memory cells) and as a direct contact electrode to the variable resistance element. This multi-functionality eliminates the need for separate intermediate electrodes, simplifying the structure while maintaining patterning precision.
2Manufacturing precision
If intermediate electrodes are used to contact variable resistance elements, then manufacturing precision is improved, but ease of manufacture deteriorates due to additional fabrication steps
Solution Approach 1:
The patent removes the intermediate electrode layer from the fabrication process. Bit lines are directly formed to contact variable resistance elements, eliminating the additional fabrication steps required to create and pattern intermediate electrodes, thereby improving ease of manufacture while maintaining contact precision.
Solution Approach 2:
Instead of forming intermediate electrodes first and then patterning bit lines to contact them, the patent inverts the approach by having bit lines directly formed and patterned to contact variable resistance elements. This simplifies the fabrication sequence and improves ease of manufacture.
3Device complexity
If a shared selecting element is used between two memory cells, then device complexity is reduced, but reliability may deteriorate due to increased stress on the shared element
Solution Approach 1:
The patent merges the selecting element function between two memory cells by using a shared bit line. This reduces device complexity by eliminating redundant selecting elements. The reliability concern is addressed through proper voltage application schemes that distribute stress appropriately across the shared element.
Solution Approach 2:
The shared bit line serves as the selecting element for two different memory cells, performing multiple functions. This multi-functionality reduces device complexity while maintaining reliability through appropriate voltage control and stress distribution during read and write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of the fabrication process, increases the integration degree of the memory device, and maintains the operating characteristics of the memory cells, leading to a more efficient and cost-effective semiconductor memory solution.
Implementation Method 1
semiconductor devices which can store data using a characteristic that they are switched between different resistant states according to an applied voltage or current
Implementation Method 2
The first selecting element layer is formed of NbO2
Data Source
AI summary
A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.