3D Stacked Memory Interconnect Layout for Signal Delay Reduction
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Solution Overview
Problem
In memory devices, signal delay occurs due to varying wire lengths connecting different chip units, which hinders storage capacity and integration, and current compensation methods increase device size and risk signal interference.
Innovation Solution
A semiconductor structure with a substrate, chip set, conductive structure, and wire where chip units are stacked vertically, electrically connected, and a wire connects the conductive structure to an external circuit, allowing simultaneous signal transmission without winding, thus reducing signal delay and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chip units are stacked vertically to increase storage capacity, then storage capacity is improved, but wire lengths connecting different chip units become different causing signal delay
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional vertical stacking, where chip units are arranged in the vertical dimension rather than spreading horizontally. This allows signals to travel through vertical interconnects (vias) between stacked chips, reducing the horizontal wire length and associated delay while maintaining high storage capacity through increased chip count.
Solution Approach 2:
The patent implements a hierarchical nested structure where multiple chip units are stacked and interconnected through vertical vias, with each chip unit containing multiple memory cells. The wire structure nests within the vertical stack, with conductive layers positioned at different heights to connect adjacent chips, creating a compact nested architecture that reduces signal path length.
2Adaptability or versatility
If wires are extended to connect distant chip units, then connectivity is improved, but wire length increases causing signal delay and potential wire fracture
Solution Approach 1:
Instead of extending wires horizontally across large distances, the patent routes signals vertically through stacked chip units using short inter-chip connections. The vertical stacking approach replaces long horizontal wire runs with short vertical vias and interconnect structures, significantly reducing wire length and the risk of wire fracture while maintaining full connectivity between all chip units.
Solution Approach 2:
The patent introduces intermediate conductive structures (vias and interconnect layers) that mediate the connection between distant chip units. Rather than using single long wires, the signal path is broken into multiple short segments connected through intermediate conductive elements, reducing stress on individual wire segments and lowering fracture risk.
3Area of stationary object
If chip units are placed closer together to reduce device size, then device size is reduced, but wires become more prone to fracture and signal interference increases
Solution Approach 1:
The patent resolves the conflict between compact size and signal interference by moving the chip arrangement into the vertical dimension. Multiple chip units are stacked with small horizontal footprints, achieving high density while maintaining adequate vertical spacing between chips. This vertical separation reduces electromagnetic interference between adjacent chips compared to horizontal placement, while the overall device footprint remains compact.
Solution Approach 2:
The patent applies different spacing and insulation characteristics to different regions of the device. Insulation layers and protective structures are strategically positioned between adjacent chip units at critical interfaces, providing localized protection against signal interference and mechanical stress without increasing overall device size. The spacing between chips is optimized locally at each interface rather than uniformly throughout.
Data Source
AI summary
A semiconductor structure includes a substrate, a chip set, a conductive structure and a wire. The substrate includes an external circuit. The chip set is disposed at one side of the substrate and includes a plurality of chip units that are spaced in a direction perpendicular to the substrate, and the chip units are electrically connected to each other. The conductive structure is disposed on at least a surface of at least one of the chip units. One end of the wire is connected to the conductive structure, and the other end extends outside of the chip units and is connected to the external circuit.